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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3311a111sm9281268eec.6.2026.09.20.01.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 01:11:02 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Shawn Guo Subject: [PATCH RESEND] arm64: dts: qcom: nord: Add more clock controller nodes Date: Sun, 20 Sep 2026 16:10:49 +0800 Message-ID: <20260920081049.2183845-1-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=W9mtxhWk c=1 sm=1 tr=0 ts=6aaf9518 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=lLTCYSv0VJgAjLIAHVUA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIwMDExNiBTYWx0ZWRfX3rK5JIFFSOTd B2felsHb7IJpKpFgYmCwtJIEpesSOOsrlBPwlQwbRZwafaFRaTruDhHwrrLdXb9QBYp7OWErcqH 4mGmm9LrOdsPGfQsZ0nIurmWYnLgwHI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIwMDExNiBTYWx0ZWRfX6Lk3khHphVm5 0OJ4rU/hGdRQQ+6JvBG51lNWFsxjtmPeffxTLZT0uFwunORpzvbTowmZnAOnJQ6/aX3Lyob2o+Y MBEU69+V2bOJHLvhUL52L44oHnhCgfQQf01VfmDbinsDg9vYKQNQl0/QQsQe4zX8IqBzzGgXp/S 5P9NkWNgiDFQVJc6rsCm1IM3C8q1Dq7JoWwSyofXktsdX4KxegF18D0Xdbopq+u5PNH6UCJUEsV vzMwGFzsgiA6+YnsUBoxoFDCbUDHq/PXeMlj+yEbg6uFs0tnpnH5LfgxBeCTkfLFJGdpd4C7zRP 5HKxqFEjQrxnncI4IRNsGwtvhVgfArzrt0BLh5q7d9gyxNg3/5Gaqw8kE0vyZXGkuJ4Imki5yp0 V3ht6/n8MjA5CDufehD990VNBffTvxtnZq17OAL3KkVoNyij8QQ9d8YAe4UaV549gbpOBDFePXL xAWeXb9BlzPn+rK4XDw== X-Proofpoint-ORIG-GUID: gbo60wZAYtegMJqxg6pgFDwv4hBlYorf X-Proofpoint-GUID: gbo60wZAYtegMJqxg6pgFDwv4hBlYorf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-20_02,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609200116 From: Taniya Das Add the GPU, camera, video, and display clock controller nodes for the Qualcomm Nord SoC, along with their required dt-bindings includes. Signed-off-by: Taniya Das Signed-off-by: Shawn Guo --- Resend to separate from Nord display DTS series. Dependencies: - Nord base DTS: https://lore.kernel.org/all/20260914031412.140856-1-shengchao.guo@oss.qualcomm.com/ arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 108 ++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index c7ac2e66632e..6dc4c871f41e 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -3,7 +3,11 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include +#include #include +#include #include #include #include @@ -835,6 +839,17 @@ hscnoc: interconnect@2000000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,nord-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&nwgcc NW_GCC_GPU_GPLL0_CLK_SRC>, + <&nwgcc NW_GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + hpass_ag_noc: interconnect@5fc0000 { compatible = "qcom,nord-hpass-ag-noc"; reg = <0x0 0x05fc0000 0x0 0x37080>; @@ -877,6 +892,99 @@ nwgcc: clock-controller@8b00000 { #power-domain-cells = <1>; }; + dispcc1: clock-controller@8d00000 { + compatible = "qcom,nord-dispcc1"; + reg = <0x0 0x08d00000 0x0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&nwgcc NW_GCC_DISP_1_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_min_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpu2cc: clock-controller@9890000 { + compatible = "qcom,nord-gpu2cc"; + reg = <0x0 0x09890000 0x0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&negcc NE_GCC_GPU_2_GPLL0_CLK_SRC>, + <&negcc NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@9ce0000 { + compatible = "qcom,nord-camcc"; + reg = <0x0 0x09ce0000 0x0 0x20000>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + clocks = <&nwgcc NW_GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,nord-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&nwgcc NW_GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,nord-dispcc0"; + reg = <0x0 0x0af00000 0x0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&nwgcc NW_GCC_DISP_0_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_min_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + tcsrcc: clock-controller@f1d9000 { compatible = "qcom,nord-tcsrcc", "syscon"; -- 2.43.0