From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Shawn Guo <shengchao.guo@oss.qualcomm.com>
Subject: [PATCH 1/3] arm64: dts: qcom: nord: Add camss node
Date: Sun, 20 Sep 2026 17:10:51 +0800 [thread overview]
Message-ID: <20260920091053.2214965-2-shengchao.guo@oss.qualcomm.com> (raw)
In-Reply-To: <20260920091053.2214965-1-shengchao.guo@oss.qualcomm.com>
From: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add the camera subsystem node for the Nord SoC with its 5 CSIPHY, 3 CSID
plus 10 CSID lite and 3 IFE plus 10 IFE lite blocks, along with their
clocks, interrupts, interconnects, SMMU stream IDs and power domains.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 64 +++++++++++
arch/arm64/boot/dts/qcom/nord.dtsi | 121 ++++++++++++++++++++
2 files changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 6dc4c871f41e..3b9fcebf7baa 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -42,6 +42,70 @@ &crypto {
status = "okay";
};
+&camss {
+ clocks = <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&nwgcc NW_GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TOP_AHB_CLK>,
+ <&camcc CAM_CC_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TOP_IFE_0_CLK>,
+ <&camcc CAM_CC_TOP_IFE_1_CLK>,
+ <&camcc CAM_CC_TOP_IFE_2_CLK>,
+ <&camcc CAM_CC_TOP_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_IFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_IFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_IFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_TPG_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "csid",
+ "csid_csiphy_rx",
+ "gcc_axi_hf",
+ "top_ahb",
+ "top_fast_ahb",
+ "top_ife0",
+ "top_ife1",
+ "top_ife2",
+ "top_ife_lite",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "tpg_csiphy_rx",
+ "qdss_debug_xo";
+
+ interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+};
+
&i2c0 {
clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index 926ccf3bbe4e..9993091effdc 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1737,6 +1737,127 @@ ipcc0: mailbox@9007000 {
#mbox-cells = <2>;
};
+ camss: isp@9b32000 {
+ compatible = "qcom,nord-camss";
+
+ reg = <0 0x09b32000 0 0x2000>,
+ <0 0x09b38800 0 0x2000>,
+ <0 0x09b3f000 0 0x2000>,
+ <0 0x09c32000 0 0x1000>,
+ <0 0x09c37000 0 0x1000>,
+ <0 0x09c3c000 0 0x1000>,
+ <0 0x09c41000 0 0x1000>,
+ <0 0x09c46000 0 0x1000>,
+ <0 0x09c4b000 0 0x1000>,
+ <0 0x09c50000 0 0x1000>,
+ <0 0x09c55000 0 0x1000>,
+ <0 0x09c5a000 0 0x1000>,
+ <0 0x09c5f000 0 0x1000>,
+ <0 0x09a92000 0 0x400>,
+ <0 0x09a93000 0 0x400>,
+ <0 0x09a94000 0 0x400>,
+ <0 0x09ab1000 0 0x4000>,
+ <0 0x09ad1000 0 0x4000>,
+ <0 0x09af1000 0 0x4000>,
+ <0 0x09c34000 0 0x2000>,
+ <0 0x09c39000 0 0x2000>,
+ <0 0x09c3e000 0 0x2000>,
+ <0 0x09c43000 0 0x2000>,
+ <0 0x09c48000 0 0x2000>,
+ <0 0x09c4d000 0 0x2000>,
+ <0 0x09c52000 0 0x2000>,
+ <0 0x09c57000 0 0x2000>,
+ <0 0x09c5c000 0 0x2000>,
+ <0 0x09c61000 0 0x2000>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csid_lite5",
+ "csid_lite6",
+ "csid_lite7",
+ "csid_lite8",
+ "csid_lite9",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4",
+ "vfe_lite5",
+ "vfe_lite6",
+ "vfe_lite7",
+ "vfe_lite8",
+ "vfe_lite9";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csid_lite5",
+ "csid_lite6",
+ "csid_lite7",
+ "csid_lite8",
+ "csid_lite9",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4",
+ "vfe_lite5",
+ "vfe_lite6",
+ "vfe_lite7",
+ "vfe_lite8",
+ "vfe_lite9";
+
+ iommus = <&apps_smmu_2 0x1401 0x20>,
+ <&apps_smmu_2 0x1460 0x00>;
+
+ status = "disabled";
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,nord-pdc",
"qcom,pdc";
--
2.43.0
next prev parent reply other threads:[~2026-09-20 9:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-20 9:10 [PATCH 0/3] arm64: dts: qcom: nord: Add camss support Shawn Guo
2026-09-20 9:10 ` Shawn Guo [this message]
2026-09-20 9:10 ` [PATCH 2/3] arm64: dts: qcom: nord-rrd: Enable " Shawn Guo
2026-09-20 9:10 ` [PATCH 3/3] arm64: dts: qcom: nord-ride-embedded: " Shawn Guo
2026-09-22 11:58 ` Shawn Guo
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