From: Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>,
Krzysztof Kozlowski <krzk@kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Cc: "Long Zhao" <longzhao@ambarella.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Linus Walleij" <linusw@kernel.org>,
"Bartosz Golaszewski" <brgl@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>, "Long Zhao" <zl020895@163.com>,
"Lee Jones" <lee@kernel.org>,
mfd@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v8 12/18] gpio: pl061: use cleanup helpers for locks
Date: Mon, 21 Sep 2026 12:23:31 +0800 [thread overview]
Message-ID: <20260921-cv75-v5-v8-12-282ff5d98dda@ambarella.com> (raw)
In-Reply-To: <20260921-cv75-v5-v8-0-282ff5d98dda@ambarella.com>
From: Long Zhao <longzhao@ambarella.com>
Convert raw_spinlock critical sections to guard() from cleanup.h.
Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
drivers/gpio/gpio-pl061.c | 19 ++++++-------------
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 2913daf46aff..c821a5117eed 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -10,6 +10,7 @@
*/
#include <linux/amba/bus.h>
#include <linux/bitops.h>
+#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
@@ -103,11 +104,9 @@ static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
- unsigned long flags;
- raw_spin_lock_irqsave(&pl061->lock, flags);
+ guard(raw_spinlock_irqsave)(&pl061->lock);
regmap_update_bits(pl061->regmap, GPIODIR, BIT(offset), 0);
- raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
@@ -116,10 +115,9 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
- unsigned long flags;
unsigned int mask = BIT(offset);
- raw_spin_lock_irqsave(&pl061->lock, flags);
+ guard(raw_spinlock_irqsave)(&pl061->lock);
regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
!!value << offset);
regmap_update_bits(pl061->regmap, GPIODIR, mask, mask);
@@ -130,7 +128,6 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
*/
regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
!!value << offset);
- raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
@@ -160,7 +157,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
int offset = irqd_to_hwirq(d);
- unsigned long flags;
unsigned int gpiois = 0, gpioibe = 0, gpioiev = 0;
unsigned int bit = BIT(offset);
@@ -176,7 +172,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
}
- raw_spin_lock_irqsave(&pl061->lock, flags);
+ guard(raw_spinlock_irqsave)(&pl061->lock);
regmap_read(pl061->regmap, GPIOIEV, &gpioiev);
regmap_read(pl061->regmap, GPIOIS, &gpiois);
@@ -236,7 +232,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
regmap_write(pl061->regmap, GPIOIBE, gpioibe);
regmap_write(pl061->regmap, GPIOIEV, gpioiev);
- raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
@@ -269,9 +264,8 @@ static void pl061_irq_mask(struct irq_data *d)
struct pl061 *pl061 = gpiochip_get_data(gc);
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
- raw_spin_lock(&pl061->lock);
+ guard(raw_spinlock)(&pl061->lock);
regmap_update_bits(pl061->regmap, GPIOIE, mask, 0);
- raw_spin_unlock(&pl061->lock);
gpiochip_disable_irq(gc, d->hwirq);
}
@@ -284,9 +278,8 @@ static void pl061_irq_unmask(struct irq_data *d)
gpiochip_enable_irq(gc, d->hwirq);
- raw_spin_lock(&pl061->lock);
+ guard(raw_spinlock)(&pl061->lock);
regmap_update_bits(pl061->regmap, GPIOIE, mask, mask);
- raw_spin_unlock(&pl061->lock);
}
/**
--
2.34.1
next prev parent reply other threads:[~2026-09-21 4:23 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 4:23 [PATCH v8 00/18] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 01/18] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 02/18] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 03/18] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 04/18] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-22 7:11 ` Linus Walleij
2026-09-22 8:28 ` zl020895
2026-10-01 7:03 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 05/18] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 06/18] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 07/18] clk: ambarella: add CV75 RCT clock controller Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 08/18] gpiolib: regmap: add write_data_after_dir quirk Long Zhao via B4 Relay
2026-09-22 7:17 ` Linus Walleij
2026-09-22 8:45 ` zl020895
2026-09-21 4:23 ` [PATCH v8 09/18] gpiolib: regmap: add gpio_regmap_get_chip() Long Zhao via B4 Relay
2026-09-21 10:35 ` Bartosz Golaszewski
2026-09-21 12:19 ` zl020895
2026-09-21 13:05 ` Bartosz Golaszewski
2026-09-21 4:23 ` [PATCH v8 10/18] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 11/18] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-09-22 7:24 ` Linus Walleij
2026-09-21 4:23 ` Long Zhao via B4 Relay [this message]
2026-09-22 7:24 ` [PATCH v8 12/18] gpio: pl061: use cleanup helpers for locks Linus Walleij
2026-09-21 4:23 ` [PATCH v8 13/18] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-09-22 7:25 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 14/18] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 15/18] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-22 7:28 ` Linus Walleij
2026-10-01 7:05 ` Linus Walleij
2026-09-21 4:23 ` [PATCH v8 16/18] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 17/18] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-21 4:23 ` [PATCH v8 18/18] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-21 10:31 ` [PATCH v8 00/18] Ambarella CV75 SoC minimal bring-up Bartosz Golaszewski
2026-09-21 11:08 ` zl020895
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