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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c331d3f2csm14091444eec.28.2026.09.20.23.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 23:20:49 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Mon, 21 Sep 2026 11:49:42 +0530 Subject: [PATCH 09/11] arm64: dts: qcom: ipq5424: Wire up PPE clock to GCC Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-ipq_clk_changes-v1-9-d242e3d49648@oss.qualcomm.com> References: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> In-Reply-To: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Konrad Dybcio , Varadarajan Narayanan , Dmitry Baryshkov , Abel Vesa , Gokul Sriram Palanisamy , Sricharan Ramabadhran , Kathiravan T Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Kathiravan Thirumoorthy , Konrad Dybcio X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDA4OSBTYWx0ZWRfX4QPUzoZA2g0U MCp6gWxqUnRNDtS/jhd+H2CmlD2TftiZH/fdO/wtPL1205990QI1o+YFLDv8zR8Bbg2H3qJ4e+s 6Y8z4OOGxkLD75lqP1FUYgOGkEOk+mi27iE2UQ2IbgFRjoFmitAiGbOXqVLKFfVM/HHKWpRMa6a 8QN0uVETK1x2mXSeV5a+CILSLsEWOHr/VeHWhKfUJf50n794mtzWLMWZoTdlFisXlwNtH2O3aW7 wEDvDGqwZIJKKJ+EJgCclLeHsDaHVRZQZmTg737/9Q0Esa16iMf8e1y/ilCTPN/j3YaeYk7gbwc aSWDr6oHEG2hzaVnDZKnzOClZd4hulrNOxg9E1E631EfLcCNYXNrYK9pKve38wMe9X3YP+nydvp 4iRKWNw8F6sV8cOeaUfJ8W8friJlBCh4DEdIVcvnqSsnsbmcmJ34cK6z+sJwPwFazxCoxMJlGnN Hs4TKAjegD3UgkveBeg== X-Proofpoint-ORIG-GUID: UX_cFsHaT6l6xgrjsXU2bwDUNH2BorRO X-Proofpoint-GUID: UX_cFsHaT6l6xgrjsXU2bwDUNH2BorRO X-Authority-Analysis: v=2.4 cv=dakVTnXe c=1 sm=1 tr=0 ts=6ab0ccc2 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=W7I2jtZzSWFJvz47EOMA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDA4OSBTYWx0ZWRfX1ife33iDShvd Kh3AnIJfggaNCI5bx9eY5WnrQmvNKEUGw0Jbx7/0PTtdlyG/7lwzrjCFVDVJmjfYu7NUnm3bCVy gxWvuiKOiqOK62vk0o2Y+SfEZISHcwU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_02,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210089 Add the PPE 375 MHz clock generated by the CMN PLL to the GCC clock controller inputs. GCC uses this clock as the source for the NSS MEMNOC clocks. Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 95e2508ac145..64a06d615d61 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -486,7 +486,8 @@ gcc: clock-controller@1800000 { <&pcie1_phy>, <&pcie2_phy>, <&pcie3_phy>, - <&ssphy_0>; + <&ssphy_0>, + <&cmn_pll IPQ5424_PPE_375MHZ_CLK>; #clock-cells = <1>; #reset-cells = <1>; #interconnect-cells = <1>; -- 2.34.1