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Nord has a single Gen5-capable QMP PCIe PHY block split into four independently-clocked and independently-resettable ports (A/B/C/D). Firmware selects the active lane topology at boot via a TCSR configuration register, and the same PHY block can appear as a single x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This is similar in spirit to the Glymur multi-PHY support already posted, except Nord's PHY registers are programmed by Linux rather than by firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init tables along with the power-up/power-down/soft-reset sequencing needed to bring each port up. The series also documents and wires up the qcom,nord-pcie compatible (reusing the existing SA8775P PCIe controller binding), and adds a CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing convergence issue in the PCIe power domain. Signed-off-by: Krishna Chaitanya Chundru --- To: Vinod Koul To: Neil Armstrong To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Chaitanya Chundru To: Lorenzo Pieralisi To: Krzysztof Wilczyński To: Manivannan Sadhasivam To: Bjorn Helgaas To: Bjorn Andersson To: Maxime Chevallier To: Philipp Zabel Cc: shengchao.guo@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: shengchao.guo@oss.qualcomm.com --- Changes in v4: - Couple of nits in dt binding & phy driver (shawn, Mani) - Add proper description for link-mode & phy-cells - Remove soc node and address cells from example (Mani) - change cgc_dis_workaround to disable_cgc (Mani) - Split common changes and nord changes (Mani) - Link to v3: https://patch.msgid.link/20260909-nord-v3-0-b0a82721c547@oss.qualcomm.com Changes in v3: - change the name to quadfurcated phy (Konrad). - remove min items and change clocks order (Krzysztof). - Factor out the common config and create overlays & try to use common symbols for glymur and nord (Konrad). - create qphy_setbit and qphy_clrbit (Qiang Yu). - and in qmp_pcie_exit() apply settings only when nocsr is present (Qiang Yu). - Link to v2: https://patch.msgid.link/20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com Changes in v2: - Fix dtbinding errors (Krzysztof) - Link to v1: https://patch.msgid.link/20260825-nord-v1-0-7c02f2b8765a@oss.qualcomm.com --- Krishna Chaitanya Chundru (6): dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding dt-bindings: pci: qcom: add Nord PCIe controller compatible PCI: qcom: Add Nord PCIe controller support phy: qcom: qmp: Move qphy_setbits/clrbits/checkbits to common header phy: qcom: qmp-pcie: Refactor common multiphy handling phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 1 + .../phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml | 267 ++++++ drivers/pci/controller/dwc/pcie-qcom.c | 16 + drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 24 - drivers/phy/qualcomm/phy-qcom-qmp-common.h | 32 + drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 24 - drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 970 +++++++++++++++++++-- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 - drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_40.h | 55 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_40.h | 14 + .../qualcomm/phy-qcom-qmp-qserdes-com-pcie-v6_40.h | 94 ++ .../phy-qcom-qmp-qserdes-txrxz-pcie-v6_40.h | 194 +++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 24 - drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 24 - drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 24 - 15 files changed, 1566 insertions(+), 229 deletions(-) --- base-commit: 5ad078139f684fa1f018fe0134812d4aa17fa53f change-id: 20260810-nord-461809f1d5ae Best regards, -- Krishna Chaitanya Chundru