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Mon, 21 Sep 2026 22:33:12 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id EA5ED480029; Mon, 21 Sep 2026 22:33:11 +0200 (CEST) From: Sebastian Reichel Date: Mon, 21 Sep 2026 22:32:44 +0200 Subject: [PATCH v2 1/8] dt-bindings: clock: rk3588: add PCLK_DDR_MON_CH clocks Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-rockchip-dfi-cleanup-v2-1-43ff34ac8599@collabora.com> References: <20260921-rockchip-dfi-cleanup-v2-0-43ff34ac8599@collabora.com> In-Reply-To: <20260921-rockchip-dfi-cleanup-v2-0-43ff34ac8599@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli On RK3588, each memory channel has its own DDR bandwidth monitor silicon, and each instance of that has its own clock gate that drives the monitor logic. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index 7528034cff56..6ea25019ebb4 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -738,6 +738,10 @@ #define I2S1_8CH_MCLKOUT_TO_IO 723 #define I2S2_2CH_MCLKOUT_TO_IO 724 #define I2S3_2CH_MCLKOUT_TO_IO 725 +#define PCLK_DDR_MON_CH0 726 +#define PCLK_DDR_MON_CH1 727 +#define PCLK_DDR_MON_CH2 728 +#define PCLK_DDR_MON_CH3 729 /* scmi-clocks indices */ -- 2.53.0