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Mon, 21 Sep 2026 22:33:12 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id F232A480038; Mon, 21 Sep 2026 22:33:11 +0200 (CEST) From: Sebastian Reichel Date: Mon, 21 Sep 2026 22:32:49 +0200 Subject: [PATCH v2 6/8] clk: rockchip: rk3588: add PCLK_DDR_MON_CH gate branches Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-rockchip-dfi-cleanup-v2-6-43ff34ac8599@collabora.com> References: <20260921-rockchip-dfi-cleanup-v2-0-43ff34ac8599@collabora.com> In-Reply-To: <20260921-rockchip-dfi-cleanup-v2-0-43ff34ac8599@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli On the Rockchip RK3588, each memory channel has some bandwidth monitoring silicon (hence the "DDR_MON"), which is driven by a clock gated by PCLK_DDR_MON_CH0/1/2/3. These clock branches were left out of the mainline clock tree until now. Add them, with the proper CRU reg bits, and the proper parent. They are given the "CLK_IGNORE_UNUSED" flag, so that older device trees with newer kernels don't turn off the clocks because they're seen as not in use. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-rk3588.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 24baa0ef9bf3..0485faf27163 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1349,6 +1349,14 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(70), 4, GFLAGS), + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_center_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(20), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH1, "pclk_ddr_mon_ch1", "pclk_center_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(20), 14, GFLAGS), + GATE(PCLK_DDR_MON_CH2, "pclk_ddr_mon_ch2", "pclk_center_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(23), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH3, "pclk_ddr_mon_ch3", "pclk_center_root", CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(23), 14, GFLAGS), GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, RK3588_CLKGATE_CON(70), 7, GFLAGS), GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, -- 2.53.0