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[82.127.110.121]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48724562aebsm25313835f8f.14.2026.09.21.08.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 08:31:35 -0700 (PDT) From: Amin Gattout Date: Mon, 21 Sep 2026 17:30:01 +0200 Subject: [PATCH v2 5/5] arm64: dts: rockchip: add vicap node to rk3576 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-vicap-rk3576-v2-5-0a4582e20c72@gmail.com> References: <20260921-vicap-rk3576-v2-0-0a4582e20c72@gmail.com> In-Reply-To: <20260921-vicap-rk3576-v2-0-0a4582e20c72@gmail.com> To: Mehdi Djait , Michael Riesch , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Amin Gattout X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790004687; l=3338; i=amin.gattout@gmail.com; s=20260818; h=from:subject:message-id; bh=ZC4qyA+QqW+G5Bs4L+6PfR/B7WGJI496vaWFRnkBXSU=; b=0LFg7TskclcAaCKsLisQlh1M5J7hMLHO+H4Vs4clqqE8Vi5mMqDn0Btt6CcQ37cSRzpVaha+6 WJotjvQpMwjD/J9lQ19LZJojwTq6AFHEacSCgvrUauDIJ1MgRuVpGdE X-Developer-Key: i=amin.gattout@gmail.com; a=ed25519; pk=MSIqDPkCOkwtyP8Fns1m+KFU9SgqoDl2mpLe18vL+hQ= Add the device tree node for the Video Capture (VICAP) unit of the RK3576 and its IOMMU, and connect the VICAP to the two MIPI CSI-2 receivers that are usable with the MIPI D-PHYs in full mode. Reviewed-by: Michael Riesch Signed-off-by: Amin Gattout --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 83 ++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index cbf8b70cc15a..0c46accf5657 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1323,6 +1323,81 @@ vdec_mmu: iommu@27b00800 { rockchip,disable-mmu-reset; #iommu-cells = <0>; }; + vicap: video-capture@27c10000 { + compatible = "rockchip,rk3576-vicap"; + reg = <0x0 0x27c10000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, + <&cru CLK_VICAP_I0CLK>, <&cru CLK_VICAP_I1CLK>, + <&cru CLK_VICAP_I2CLK>, <&cru CLK_VICAP_I3CLK>, + <&cru CLK_VICAP_I4CLK>; + clock-names = "aclk", "hclk", "dclk", + "iclk", "iclk1", "iclk2", "iclk3", "iclk4"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3576_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, + <&cru SRST_VICAP_I0CLK>, <&cru SRST_VICAP_I1CLK>, + <&cru SRST_VICAP_I2CLK>, <&cru SRST_VICAP_I3CLK>, + <&cru SRST_VICAP_I4CLK>; + reset-names = "arst", "hrst", "drst", + "irst0", "irst1", "irst2", "irst3", "irst4"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0x0>; + }; + + vicap_mipi0: port@1 { + reg = <0x1>; + }; + + vicap_mipi1: port@2 { + reg = <0x2>; + + vicap_mipi1_input: endpoint { + remote-endpoint = <&csi1_output>; + }; + }; + + vicap_mipi2: port@3 { + reg = <0x3>; + }; + + vicap_mipi3: port@4 { + reg = <0x4>; + + vicap_mipi3_input: endpoint { + remote-endpoint = <&csi3_output>; + }; + }; + + vicap_mipi4: port@5 { + reg = <0x5>; + }; + + vicap_toisp0: port@10 { + reg = <0x10>; + }; + }; + }; + + vicap_mmu: iommu@27c10800 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27c10800 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3576_PD_VI>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; csi1: csi@27c90000 { compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2"; @@ -1346,6 +1421,10 @@ csi1_in: port@0 { csi1_out: port@1 { reg = <1>; + + csi1_output: endpoint { + remote-endpoint = <&vicap_mipi1_input>; + }; }; }; }; @@ -1372,6 +1451,10 @@ csi3_in: port@0 { csi3_out: port@1 { reg = <1>; + + csi3_output: endpoint { + remote-endpoint = <&vicap_mipi3_input>; + }; }; }; }; -- 2.43.0