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[92.247.61.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fc585920fsm587218725e9.4.2026.09.21.02.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 02:07:42 -0700 (PDT) From: Petko Manolov To: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, arnemaximilian.richter@draeger.com, martynas.grybauskas@draeger.com, Petko Manolov Subject: [PATCH v7 0/3] arm: dts: altera: add Draeger M48 CPU board Date: Mon, 21 Sep 2026 12:07:30 +0300 Message-ID: <20260921090735.3174292-1-petko.manolov@konsulko.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera SoCFPGA Cyclone V” board variant. It has both (the SoC and FPGA) on the same carrier and they are cross-monitoring each other. The SoCFPGA boots independently off qspi flash. This is the SoCFPGA devicetree part. new in v7: - replaced module with board as this seems to be confusing to some; - add Acked-by: Conor Dooley tag; Petko Manolov (3): dt-bindings: vendor-prefixes: add Draeger AG dt-bindings: arm: altera: add Draeger M48 dual-cpu board arm: dts: altera: add Draeger M48 CPU Module .../devicetree/bindings/arm/altera.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm/boot/dts/intel/socfpga/Makefile | 1 + .../socfpga/socfpga_cyclone5_draeger_m48.dts | 123 ++++++++++++++++++ 4 files changed, 127 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts -- 2.47.3