[PATCH v2 2/9] dt-bindings: power: Add r8a774a3 SYSC power domain definitions

[Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>]

Add power domain indices for the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3)
SoC.

Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
- Updated commit message
- Renamed file to include vendor prefix
- Added vendor prefix to include macros
- Added Reviewed-by tag

 .../dt-bindings/power/renesas,r8a774a3-sysc.h | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 include/dt-bindings/power/renesas,r8a774a3-sysc.h

diff --git a/include/dt-bindings/power/renesas,r8a774a3-sysc.h b/include/dt-bindings/power/renesas,r8a774a3-sysc.h
new file mode 100644
index 000000000000..ddee6812e9a4
--- /dev/null
+++ b/include/dt-bindings/power/renesas,r8a774a3-sysc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__
+#define __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A3_PD_CA57_CPU0		 0
+#define R8A774A3_PD_CA57_CPU1		 1
+#define R8A774A3_PD_CA53_CPU0		 5
+#define R8A774A3_PD_CA53_CPU1		 6
+#define R8A774A3_PD_CA53_CPU2		 7
+#define R8A774A3_PD_CA53_CPU3		 8
+#define R8A774A3_PD_CA57_SCU		12
+#define R8A774A3_PD_A3VC		14
+#define R8A774A3_PD_3DG_A		17
+#define R8A774A3_PD_3DG_B		18
+#define R8A774A3_PD_CA53_SCU		21
+#define R8A774A3_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774A3_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ */
-- 
2.34.1