Re: [PATCH v2 2/2] arm64: dts: qcom: nord: wire up GPI DMA for QUP I2C/SPI engines

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: qcom: SPI DMA properties mistakenly added to UART nodes
--

commit be91916b8a47fc6278b780bd5f1d5c34e90bd488
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

arm64: dts: qcom: nord: wire up GPI DMA for QUP I2C/SPI engines

This commit adds DMA phandles to I2C and SPI QUPv3 serial engine nodes
in the device tree.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index 9f4e0e1498c32..906e4e67f03c7 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi

[ ... ]

> @@ -1184,6 +1220,10 @@ uart0: serial@980000 {
>  				reg = <0x0 0x00980000 0x0 0x4000>;
>  				interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
>  
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +
>  				status = "disabled";
>  			};

[Severity: High]
Does this mistakenly add the SPI DMA configuration to the uart0 node
instead of a spi node?

In the Qualcomm GPI DMA driver, gpi_terminate_all() determines how to
terminate channels based on the protocol. If the protocol is QCOM_GPI_UART,
it terminates the TX or RX channel independently. If the protocol is set
to QCOM_GPI_SPI, it assumes a synchronous protocol and forces both the TX
and RX channels to be terminated and reset in lockstep.

If QCOM_GPI_SPI is applied to asynchronous uart nodes, won't this cause
data loss? For example, if the UART driver terminates one channel to flush
an RX timeout, the DMA driver will silently reset the other active TX channel
mid-transfer, dropping characters.

This same QCOM_GPI_SPI configuration appears to be mistakenly applied to
uart1, uart2, uart3, uart7, uart8, uart11, and uart12 later in this patch.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260921-nord-gpi-dts-v2-0-4f297c983b94@oss.qualcomm.com?part=2