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Introduce new PSIL_EP_PDMA_XYMF type for channels that have multiple selectable fifos. Also add a new fifo_id field to psil_endpoint_config to specify the selectable fifo_id. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/Makefile | 3 +- drivers/dma/ti/k3-psil-am62l.c | 169 +++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-psil-priv.h | 5 + drivers/dma/ti/k3-psil.c | 78 ++++++++++++++- include/linux/dma/k3-psil.h | 3 + 5 files changed, 253 insertions(+), 5 deletions(-) create mode 100644 drivers/dma/ti/k3-psil-am62l.c diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 3b91c02e55eaf..41bfba944dc6c 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -14,6 +14,7 @@ k3-psil-lib-objs := k3-psil.o \ k3-psil-am62.o \ k3-psil-am62a.o \ k3-psil-j784s4.o \ - k3-psil-am62p.o + k3-psil-am62p.o \ + k3-psil-am62l.o obj-$(CONFIG_TI_K3_PSIL) += k3-psil-lib.o obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o diff --git a/drivers/dma/ti/k3-psil-am62l.c b/drivers/dma/ti/k3-psil-am62l.c new file mode 100644 index 0000000000000..ee77fae3787a4 --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62l.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x, ch) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = ch, \ + .default_flow_id = -1, \ + }, \ + } + +#define PSIL_PDMA_XYMF_TR(x, ch, fifo) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XYMF, \ + .mapped_channel_id = ch, \ + .default_flow_id = -1, \ + .fifo_id = fifo, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x, ch) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .mapped_channel_id = ch, \ + .pkt_mode = 1, \ + .default_flow_id = -1 \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + .pkt_mode = 1, \ + .needs_epib = 1, \ + .psd_size = 16, \ + .mapped_channel_id = ch, \ + .flow_start = flow_base, \ + .flow_num = flow_cnt, \ + .default_flow_id = flow_base, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x, ch) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_PDMA_XY, \ + .pdma_acc32 = 1, \ + .pdma_burst = 1, \ + .mapped_channel_id = ch, \ + .default_flow_id = -1 \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62l_src_ep_map[] = { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400, 0), + PSIL_PDMA_XY_PKT(0x4401, 2), + PSIL_PDMA_XY_PKT(0x4402, 4), + PSIL_PDMA_XY_PKT(0x4403, 6), + PSIL_PDMA_XY_PKT(0x4404, 8), + PSIL_PDMA_XY_PKT(0x4405, 10), + PSIL_PDMA_XY_PKT(0x4406, 12), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4300, 16, 0), + PSIL_PDMA_XYMF_TR(0x4300, 18, 1), + PSIL_PDMA_XYMF_TR(0x4300, 20, 2), + PSIL_PDMA_XYMF_TR(0x4300, 22, 3), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4301, 24, 0), + PSIL_PDMA_XYMF_TR(0x4301, 26, 1), + PSIL_PDMA_XYMF_TR(0x4301, 28, 2), + PSIL_PDMA_XYMF_TR(0x4301, 30, 3), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4302, 32, 0), + PSIL_PDMA_XYMF_TR(0x4302, 34, 1), + PSIL_PDMA_XYMF_TR(0x4302, 36, 2), + PSIL_PDMA_XYMF_TR(0x4302, 38, 3), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0x4303, 40, 0), + PSIL_PDMA_XYMF_TR(0x4303, 42, 1), + PSIL_PDMA_XYMF_TR(0x4303, 44, 2), + PSIL_PDMA_XYMF_TR(0x4303, 46, 3), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500, 48), + PSIL_PDMA_MCASP(0x4501, 50), + PSIL_PDMA_MCASP(0x4502, 52), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0x4700, 65), + /* PDMA_MAIN0 - ADC */ + PSIL_PDMA_XY_TR(0x4503, 80), + PSIL_PDMA_XY_TR(0x4504, 81), + PSIL_ETHERNET(0x4600, 96, 96, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62l_dst_ep_map[] = { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xC400, 1), + PSIL_PDMA_XY_PKT(0xC401, 3), + PSIL_PDMA_XY_PKT(0xC402, 5), + PSIL_PDMA_XY_PKT(0xC403, 7), + PSIL_PDMA_XY_PKT(0xC404, 9), + PSIL_PDMA_XY_PKT(0xC405, 11), + PSIL_PDMA_XY_PKT(0xC406, 13), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC300, 17, 0), + PSIL_PDMA_XYMF_TR(0xC300, 19, 1), + PSIL_PDMA_XYMF_TR(0xC300, 21, 2), + PSIL_PDMA_XYMF_TR(0xC300, 23, 3), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC301, 25, 0), + PSIL_PDMA_XYMF_TR(0xC301, 27, 1), + PSIL_PDMA_XYMF_TR(0xC301, 29, 2), + PSIL_PDMA_XYMF_TR(0xC301, 31, 3), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC302, 33, 0), + PSIL_PDMA_XYMF_TR(0xC302, 35, 1), + PSIL_PDMA_XYMF_TR(0xC302, 37, 2), + PSIL_PDMA_XYMF_TR(0xC302, 39, 3), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XYMF_TR(0xC303, 41, 0), + PSIL_PDMA_XYMF_TR(0xC303, 43, 1), + PSIL_PDMA_XYMF_TR(0xC303, 45, 2), + PSIL_PDMA_XYMF_TR(0xC303, 47, 3), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xC500, 49), + PSIL_PDMA_MCASP(0xC501, 51), + PSIL_PDMA_MCASP(0xC502, 53), + /* PDMA_MAIN0 - SHA */ + PSIL_PDMA_XY_TR(0xC700, 64), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0xC701, 66), + /* PDMA_MAIN0 - CRC32 - CH0-1 */ + PSIL_PDMA_XYMF_TR(0xC702, 67, 0), + PSIL_PDMA_XYMF_TR(0xC702, 68, 1), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 64, 64, 2), + PSIL_ETHERNET(0xc601, 66, 66, 2), + PSIL_ETHERNET(0xc602, 68, 68, 2), + PSIL_ETHERNET(0xc603, 70, 70, 2), + PSIL_ETHERNET(0xc604, 72, 72, 2), + PSIL_ETHERNET(0xc605, 74, 74, 2), + PSIL_ETHERNET(0xc606, 76, 76, 2), + PSIL_ETHERNET(0xc607, 78, 78, 2), +}; + +struct psil_ep_map am62l_ep_map = { + .name = "am62l", + .src = am62l_src_ep_map, + .src_count = ARRAY_SIZE(am62l_src_ep_map), + .dst = am62l_dst_ep_map, + .dst_count = ARRAY_SIZE(am62l_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index a577be97e3447..970afd46a79e6 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -35,6 +35,10 @@ struct psil_ep_map { }; struct psil_endpoint_config *psil_get_ep_config(u32 thread_id); +struct psil_endpoint_config *psil_get_ep_config_by_id(u32 channel_id, + bool is_pktdma, + u32 *thread_id, + bool *dev_to_mem); /* SoC PSI-L endpoint maps */ extern struct psil_ep_map am654_ep_map; @@ -46,5 +50,6 @@ extern struct psil_ep_map am62_ep_map; extern struct psil_ep_map am62a_ep_map; extern struct psil_ep_map j784s4_ep_map; extern struct psil_ep_map am62p_ep_map; +extern struct psil_ep_map am62l_ep_map; #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index c4b6f0df46861..580fc553e23fa 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -28,6 +28,7 @@ static const struct soc_device_attribute k3_soc_devices[] = { { .family = "J784S4", .data = &j784s4_ep_map }, { .family = "AM62PX", .data = &am62p_ep_map }, { .family = "J722S", .data = &am62p_ep_map }, + { .family = "AM62LX", .data = &am62l_ep_map }, { /* sentinel */ } }; @@ -71,12 +72,68 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id) } EXPORT_SYMBOL_GPL(psil_get_ep_config); +struct psil_endpoint_config *psil_get_ep_config_by_id(u32 channel_id, + bool is_pktdma, + u32 *thread_id, + bool *dev_to_mem) +{ + int i; + + mutex_lock(&ep_map_mutex); + if (!soc_ep_map) { + const struct soc_device_attribute *soc; + + soc = soc_device_match(k3_soc_devices); + if (soc) { + soc_ep_map = soc->data; + } else { + pr_err("PSIL: No compatible machine found for map\n"); + mutex_unlock(&ep_map_mutex); + return ERR_PTR(-ENOTSUPP); + } + } + + if (soc_ep_map->src) { + for (i = 0; i < soc_ep_map->src_count; i++) { + struct psil_ep *ep = &soc_ep_map->src[i]; + + if (ep->ep_config.mapped_channel_id != (s16)channel_id) + continue; + if ((bool)ep->ep_config.pkt_mode != is_pktdma) + continue; + *thread_id = ep->thread_id; + *dev_to_mem = true; + mutex_unlock(&ep_map_mutex); + return &ep->ep_config; + } + } + + if (soc_ep_map->dst) { + for (i = 0; i < soc_ep_map->dst_count; i++) { + struct psil_ep *ep = &soc_ep_map->dst[i]; + + if (ep->ep_config.mapped_channel_id != (s16)channel_id) + continue; + if ((bool)ep->ep_config.pkt_mode != is_pktdma) + continue; + *thread_id = ep->thread_id; + *dev_to_mem = false; + mutex_unlock(&ep_map_mutex); + return &ep->ep_config; + } + } + + mutex_unlock(&ep_map_mutex); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL_GPL(psil_get_ep_config_by_id); + int psil_set_new_ep_config(struct device *dev, const char *name, struct psil_endpoint_config *ep_config) { struct psil_endpoint_config *dst_ep_config; struct of_phandle_args dma_spec; - u32 thread_id; + u32 thread_id = 0; int index; if (!dev || !dev->of_node) @@ -90,9 +147,22 @@ int psil_set_new_ep_config(struct device *dev, const char *name, index, &dma_spec)) return -ENOENT; - thread_id = dma_spec.args[0]; - - dst_ep_config = psil_get_ep_config(thread_id); + if (of_device_is_compatible(dma_spec.np, "ti,am62l-dmss-pktdma")) { + bool dev_to_mem; + + dst_ep_config = psil_get_ep_config_by_id(dma_spec.args[0], + true, + &thread_id, &dev_to_mem); + } else if (of_device_is_compatible(dma_spec.np, "ti,am62l-dmss-bcdma")) { + bool dev_to_mem; + + dst_ep_config = psil_get_ep_config_by_id(dma_spec.args[2], + false, + &thread_id, &dev_to_mem); + } else { + thread_id = dma_spec.args[0]; + dst_ep_config = psil_get_ep_config(thread_id); + } if (IS_ERR(dst_ep_config)) { pr_err("PSIL: thread ID 0x%04x not defined in map\n", thread_id); diff --git a/include/linux/dma/k3-psil.h b/include/linux/dma/k3-psil.h index 5f106d852f1cf..36e347311f8b2 100644 --- a/include/linux/dma/k3-psil.h +++ b/include/linux/dma/k3-psil.h @@ -35,6 +35,7 @@ enum udma_tp_level { enum psil_endpoint_type { PSIL_EP_NATIVE = 0, PSIL_EP_PDMA_XY, + PSIL_EP_PDMA_XYMF, PSIL_EP_PDMA_MCAN, PSIL_EP_PDMA_AASRC, }; @@ -78,6 +79,8 @@ struct psil_endpoint_config { u16 flow_start; u16 flow_num; s16 default_flow_id; + /* XYMF FIFO index (0-3 for CS0-CS3), Only for PSIL_EP_PDMA_XYMF */ + u8 fifo_id; }; int psil_set_new_ep_config(struct device *dev, const char *name, -- 2.54.0