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Tue, 22 Sep 2026 03:16:09 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f294e4acsm4141064c88.1.2026.09.22.03.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 03:16:08 -0700 (PDT) From: Mohammad Rafi Shaik To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] arm64: dts: qcom: glymur-crd: Enable DMIC4 and DMIC5 on CRD Date: Tue, 22 Sep 2026 15:45:50 +0530 Message-Id: <20260922101550.2216689-1-mohammad.rafi.shaik@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: z4zs80QTs9kdyK4ycjHhgNKDW32tmmef X-Proofpoint-GUID: z4zs80QTs9kdyK4ycjHhgNKDW32tmmef X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDE0NyBTYWx0ZWRfX1C8bpW3689JR /Zy4yUy6G5+vKVNXxk5JUizv/d1ciOFZLbcXj+xIPmlMmZQ3Q8sh9CDdeRhvpkQ7YU4csUa6PPf 9kvmNw/27MwkQfe1I9e0eeTK4bbgqCIeKwB4dPPydFClMLO8fUtsPiAWCvPYqMYC+LI3rp8bVo/ v69JXOjvFyaR0R5WyAgj9j9um8hyCBauFxWaFJeB2u05kQi11QfOM463KZg3U9Aoj2tR8KjgRco LCgrn+QYVBR91V1ZZdDFEB6Gyk06a0k0aCKexufITTeCYsdhkNZ8oSXA1bIqDJF0jPBMjnjPdp/ ga1oWAqnZZkLFeZ3TFye6rEGHeT4wVEM4wPuOHVnVdY2RBs5BCcRY+xiBky4fT0E7eP51xOMpLl PgZf4GRwb9FN3V3U47y1GyQd/HdVKuFAUnwiCy2Mwbmo47YT7RdZmDwufefiHtqLRTfOg0hvXQQ Hr07ihytGdwEsY/GZLg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDE0NyBTYWx0ZWRfXx2hlCX/fLGXU HmmX4JdTOCPqJowba6juJU4D2QCPmBsrXafc6HbA+290AG4rJBJQcZVYwwnaq+9DtYRZFx9ObKf nR++NMoAlsUk2mIcTVg3G8IDujGiBO8= X-Authority-Analysis: v=2.4 cv=TvFzFzXh c=1 sm=1 tr=0 ts=6ab2556f cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=x1nICoucR8wNQKwiGQYA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_07,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220147 Add the LPASS LPI pinctrl state for the third DMIC clock line, which drives DMIC4 and DMIC5. CRD has additional digital microphones connected to this clock line, so reference the new pinctrl state from the VA macro and route the microphone bias supply to DMIC4 and DMIC5 to make them usable. Signed-off-by: Mohammad Rafi Shaik --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index ccdc322157e0..02e342ecfe4a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -247,7 +247,9 @@ sound { "VA DMIC0", "vdd-micb", "VA DMIC1", "vdd-micb", "VA DMIC2", "vdd-micb", - "VA DMIC3", "vdd-micb"; + "VA DMIC3", "vdd-micb", + "VA DMIC4", "vdd-micb", + "VA DMIC5", "vdd-micb"; wsa-dai-link { link-name = "WSA Playback"; @@ -695,7 +697,7 @@ touchscreen@38 { }; &lpass_vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&dmic45_default>; pinctrl-names = "default"; qcom,dmic-sample-rate = <4800000>; vdd-micb-supply = <&vreg_l1b_e0_1p8>; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index de7c395d9c35..c941b473ce25 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4768,6 +4768,22 @@ data-pins { }; }; + dmic45_default: dmic45-default-state { + clk-pins { + pins = "gpio17"; + function = "dmic4_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio18"; + function = "dmic4_data"; + drive-strength = <8>; + input-enable; + }; + }; + wsa_swr_active: wsa-swr-active-state { clk-pins { pins = "gpio10"; -- 2.34.1