From: sashiko-bot@kernel.org
To: "Mohammad Rafi Shaik" <mohammad.rafi.shaik@oss.qualcomm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v1] arm64: dts: qcom: glymur-crd: Enable DMIC4 and DMIC5 on CRD
Date: Tue, 22 Sep 2026 10:27:51 +0000 [thread overview]
Message-ID: <20260922102752.23F681F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260922101550.2216689-1-mohammad.rafi.shaik@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] sound: qcom: DMIC pinctrl and DAPM route mismatch leaves mics unclocked
--
commit acf2021d4b3109886871e1b20f566cf0a1e65f99
Author: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
arm64: dts: qcom: glymur-crd: Enable DMIC4 and DMIC5 on CRD
Add the LPASS LPI pinctrl state for the third DMIC clock line, which
drives DMIC4 and DMIC5.
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> index e27c697e31702..3f600b924a31d 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
> @@ -247,7 +247,9 @@ sound {
> "VA DMIC0", "vdd-micb",
> "VA DMIC1", "vdd-micb",
> "VA DMIC2", "vdd-micb",
> - "VA DMIC3", "vdd-micb";
> + "VA DMIC3", "vdd-micb",
> + "VA DMIC4", "vdd-micb",
> + "VA DMIC5", "vdd-micb";
[Severity: Medium]
Will this DAPM route configuration mismatch the pinctrl configuration below?
Requesting DAPM audio routes for VA DMIC4 and VA DMIC5 causes the VA Macro
codec to enable the 3rd DMIC clock line. However, the pinctrl state configured
in glymur.dtsi targets the 4th clock line. As a result, the newly added
microphones might fail to capture audio, returning only silence.
[ ... ]
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f04058d2e0891..891377f38dcb5 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -4437,6 +4437,22 @@ data-pins {
> };
> };
>
> + dmic45_default: dmic45-default-state {
> + clk-pins {
> + pins = "gpio17";
> + function = "dmic4_clk";
[Severity: Medium]
Should this function be dmic3_clk instead?
The commit message states the intent is to enable the third DMIC clock line
for DMIC4 and DMIC5. Configuring dmic4_clk on gpio17 here assigns it to
the fourth DMIC clock line, which mismatches the VA Macro codec that expects
the third clock line. In other Qualcomm devicetrees, dmic45_default correctly
configures the dmic3_clk function.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260922101550.2216689-1-mohammad.rafi.shaik@oss.qualcomm.com?part=1
prev parent reply other threads:[~2026-09-22 10:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 10:15 [PATCH v1] arm64: dts: qcom: glymur-crd: Enable DMIC4 and DMIC5 on CRD Mohammad Rafi Shaik
2026-09-22 10:27 ` sashiko-bot [this message]
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