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[46.193.35.178]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4886876c500sm374681f8f.19.2026.09.22.11.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 11:44:58 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Abel Vesa , Brian Masney , Jerome Brunet , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/4] dt-bindings: clock: Add LPASSCC and reset controller for Glymur Date: Tue, 22 Sep 2026 19:44:23 +0100 Message-ID: <20260922184425.56114-3-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> References: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX+DvGC1HZ2aUd ntOZDk8b90tWp/+uQg3AXSdMoTopdr5NVkJrHCZM/NPAgEnUwBAYAsTkao2B3u6/aKl4puKb6vv NkfwHZRgU5eRUdfeFdC59ZtqmLGalecBqrhkieQ1eTvkKLzIIUveOX3GPkF/bovWNzDGv2XlM2v kKohOVIHZQGbECrJaKvyMuZCjMwi0bFH+31W8yVB9z1dZWxcQxwPlPbW2FcEegq/JX9hQqgRhQe LZGwVhV2Hvl0yZZBgUZ4nI+MPNIdyFRBLuMCATTpig92tyPMGgn+V6JPZikp6DM8IgeK+Ks8N8r 0UcC33NvlkGUPILPSK13JQYmWr9J0ezCDBnxe2SOsYEGbixlH9VgPoWt3Un5K/bdVklJ5J2uy1w 9emVHsxP87NPTyxK5HgjfAGKhlvhH49wyP63+1jQqBbEe2B3se9uMjNtrKfSglQzj9QvSVXM0D3 koAb3/4gyqLVt5CY6iQ== X-Authority-Analysis: v=2.4 cv=VKdIDNPX c=1 sm=1 tr=0 ts=6ab2ccad cx=c_pps a=wuOIiItHwq1biOnFUQQHKA==:117 a=Hji71o54RgNgZYqDgtlrhw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=-l7Lzzg0JijIaF3KBckA:9 a=XD7yVLdPMpWraOa8Un9W:22 X-Proofpoint-GUID: bbBhXMW403SxM9puLM4J6xE_QBNid59B X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX1/kuj1A/mwiw 1yK8GQYSB9jL8Y9RzU/tJ4VsYfCYmDtLZMtF09bMyv++MlDSSX0GRuhzN0XU3XBl7aoPdFu8TQQ GBz4ErNPsX7ZZJE1JnTdhNlCgjaLJTQ= X-Proofpoint-ORIG-GUID: bbBhXMW403SxM9puLM4J6xE_QBNid59B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220275 The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/clock/qcom,glymur-lpasscc.yaml | 10 ++++++++++ include/dt-bindings/clock/qcom,glymur-lpasscc.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml index c047c0174a93..916ab1b3dbee 100644 --- a/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - qcom,glymur-lpassaudiocc + - qcom,glymur-lpasscc reg: maxItems: 1 @@ -47,4 +48,13 @@ examples: #clock-cells = <1>; #reset-cells = <1>; }; + + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,glymur-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; ... diff --git a/include/dt-bindings/clock/qcom,glymur-lpasscc.h b/include/dt-bindings/clock/qcom,glymur-lpasscc.h index 3006b12e385e..3fc8e7313cab 100644 --- a/include/dt-bindings/clock/qcom,glymur-lpasscc.h +++ b/include/dt-bindings/clock/qcom,glymur-lpasscc.h @@ -13,4 +13,7 @@ #define LPASS_AUDIO_SWR_WSA3_CGCR 3 #define LPASS_AUDIO_SWR_WSA4_CGCR 4 +/* LPASS CC CSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + #endif -- 2.53.0