Re: [PATCH 3/5] arm64: dts: qcom: Introduce Maili SoC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] dts: reserved-memory overlap between mpss_mem and other regions
- [Medium] dts: invalid topology, all CPUs share a single l2_0 cache node
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commit 81315838a00d887952d320c67bfae01521f7328e
Author: Jingyi Wang <jingyi.wang@oss.qualcomm.com>

arm64: dts: qcom: Introduce Maili SoC

This commit introduces the device tree file for the Qualcomm Snapdragon
Maili SoC. It defines CPUs, PSCI idle states, interrupt controllers, timers,
reserved memory regions, interconnects, and other hardware peripherals.

> diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
> new file mode 100644
> index 0000000000000..886d307e536be
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/maili.dtsi
> @@ -0,0 +1,6956 @@
[ ... ]
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu6: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,oryon-3-0";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&l2_0>;

[Severity: Medium]
Does this topology accurately reflect the hardware? The l2_0 cache is
defined later under cpu0 but referenced here and by all other cores, implying
all CPUs across all clusters share a single private L2 cache. Each core or
cluster must have its own topologically correct L2 cache node for the
scheduler to make correct migration decisions.

[ ... ]
> +		pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
> +			reg = <0x0 0x81f00000 0x0 0x100000>;
> +			no-map;
> +		};
> +
> +		smem_mem: smem@82700000 {
> +			compatible = "qcom,smem";
> +			reg = <0x0 0x82700000 0x0 0x400000>;
> +			hwlocks = <&tcsr_mutex 3>;
> +			no-map;
> +		};
> +
> +		dsm_partition_1_mem: dsm-partition-1@83500000 {
> +			reg = <0x0 0x83500000 0x0 0x5180000>;
> +			no-map;
> +		};
> +
> +		dsm_partition_2_mem: dsm-partition-2@88680000 {
> +			reg = <0x0 0x88680000 0x0 0x1700000>;
> +			no-map;
> +		};
> +
> +		mpss_mem: mpss@89e00000 {
> +			reg = <0x0 0x89e00000 0x0 0x10400000>;
> +			no-map;
> +		};

[Severity: High]
Does the size of mpss_mem intentionally overlap with the following memory
blocks? The mpss_mem region is defined from 0x89e00000 with a size of
0x10400000, spanning up to 0x9a200000. 

This engulfs the subsequent q6-mpss-dtb, ipa-fw, ipa-gsi, gpu-microcode,
camera regions, and partially overlaps camera-2. Memblock reservations must
be disjoint to prevent early boot reservation failures.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com?part=3