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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a07ddaf4f5sm2102026a91.4.2026.09.22.19.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 19:41:47 -0700 (PDT) From: Wangao Wang Date: Wed, 23 Sep 2026 10:41:12 +0800 Subject: [PATCH v2 2/6] dt-bindings: media: qcom,maili-iris: Add Maili video codec Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260923-add_iris_for_maili-v2-2-7223738e330d@oss.qualcomm.com> References: <20260923-add_iris_for_maili-v2-0-7223738e330d@oss.qualcomm.com> In-Reply-To: <20260923-add_iris_for_maili-v2-0-7223738e330d@oss.qualcomm.com> To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Abhinav Kumar , Hans Verkuil , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790131292; l=7742; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=+T5vulQEyMVm6P9sXfAjnNyXQcGFVgyBTnNOo30l8nE=; b=xs8h2an6tuCJt9Fow62KGRLwQDXcITZvAjw0qf5hEjCu+Q5qUSyhg0bs/dIzcUAkFh8f0BbUr 7QFBDzokvf0DYfo6QQdevD+ZOSy8WYnTziMEde9O/PpM/O8bPEm2djw X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Authority-Analysis: v=2.4 cv=SJnXx+vH c=1 sm=1 tr=0 ts=6ab33c6d cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=MWoX49SKP4xWF05JRPIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: 59epJZlBTUMqOloiMwHkHcEUir39unjy X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAxMCBTYWx0ZWRfX3s9+4QBjj3Eg G5I6NQiZuXyQPXOo2CAfWaS4bwKwrWSlcRrmMIIfMe9TmKoTc3uWv20pN2uUxdhPnRHh8DpChW3 HoLfPGNzF+1SKWdj4LioCBBdS08Mzs8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAxMCBTYWx0ZWRfX3jeYrcWVRF6Z pMTL3f0gcfjmICp8ddTkQXYzALy/kLq2ZnNaH7+zAwrUtGChYySWfZcRwwN1+dBweTyhKORhLte do6v4U3J2esxRVSKTNsXl9aXcnj1XPrHr2f+Lg30+eexp+bzt64edVarC1OR2biYxpt7JE5PDOM TGHL80TnOpTY9gRxE9dqBQQWQNIhwgEkUHTODOHBKmyHnlxpf6v9Wopn/FkeBkYySa/5JjiSWPi ZSObhYI2JswJl4kQP0L/wH6CKOYDufP5ZkfNzF/giMBkOtvU3CYFmX1VmHNFDldBDtaelNRxs45 yQOfm3kOiQ8AdH7LARGAo4IqbCSYEpx8rbrQyfMl2M4qnupOQEdapgoKi/5Kgsst+9O2df+07FI w1PWbIiR7Luacbcn8fd2pvzWzhmTb88gBvJdntIcdkCBXt2zxQ1ko33UBvT4BSjGqbziCL2u7rW gRFFXebnBM+GJOgltQg== X-Proofpoint-ORIG-GUID: 59epJZlBTUMqOloiMwHkHcEUir39unjy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230010 Add a devicetree binding for the Iris4 video encoder and decoder block found on the Qualcomm Maili SoC. Compared to the Iris3 generation, this block has - separate clocks for BSE (Bitstream Engine) and VPP (Video Processing Pipeline). - power domain for VPP (Video Processing Pipeline). - different reset lines. Signed-off-by: Wangao Wang --- .../devicetree/bindings/media/qcom,maili-iris.yaml | 229 +++++++++++++++++++++ 1 file changed, 229 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml b/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4ddc4df8481b52661b314821a9fac68870d8ca6c --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml @@ -0,0 +1,229 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,maili-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Maili SoC Iris video encoder and decoder + +maintainers: + - Vikash Garodia + - Dikshita Agarwal + +description: + The Iris video processing unit on Qualcomm Maili SoC is a video encode and + decode accelerator. + +properties: + compatible: + enum: + - qcom,maili-iris + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 8 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + - const: iface1 + - const: core_freerun + - const: vcodec0_core_freerun + - const: vcodec_bse + - const: vcodec_vpp0 + + firmware-name: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + power-domains: + maxItems: 5 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vpp0 + + resets: + maxItems: 4 + + reset-names: + items: + - const: bus0 + - const: bus1 + - const: core + - const: vcodec0_core + + iommus: + maxItems: 4 + + dma-coherent: true + + operating-points-v2: true + + opp-table: + type: object + +required: + - compatible + - dma-coherent + - interconnects + - interconnect-names + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + video-codec@2000000 { + compatible = "qcom,maili-iris"; + reg = <0x02000000 0xf0000>; + + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0B_CLK>, + <&videocc VIDEO_CC_MVS0_VPP0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "vcodec_bse", + "vcodec_vpp0"; + + dma-coherent; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IRIS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + memory-region = <&video_mem>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS0_VPP0_GDSC>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vpp0"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core"; + + operating-points-v2 = <&iris_opp_table>; + + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x0 0x0 0xffc00000>; + + non-pixel { + iommus = <&apps_smmu 0x1540 0x0000>, + <&apps_smmu 0x1620 0x0000>, + <&apps_smmu 0x1544 0x0000>; + iommu-ranges = <0x25800000 0xda400000>; + }; + + pixel { + iommus = <&apps_smmu 0x1543 0x0000>; + }; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_low_svs_d2>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 338000000 507000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000 420000000 630000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 444000000 666000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000 533000000 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000 630000000 1104000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000 630000000 1260000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000 800000000 1260000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l3>; + }; + }; + }; -- 2.43.0