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Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 1 + 4 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index de576816ec7c..83c6f257f478 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -2849,6 +2849,7 @@ static const struct adreno_info a8xx_gpus[] = { .gbif_cx = a850_gbif, .max_slices = 3, .gmu_chipid = 0x80b0100, + .thinmem_config = 14, .bcms = (const struct a6xx_bcm[]) { { .name = "SH0", .buswidth = 32 }, { .name = "MC0", .buswidth = 4 }, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index b50c57f427b4..43273e5f8b5b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -42,6 +42,7 @@ struct cpu_gpu_lock { * @hwcg: hw clock gating register sequence * @protect: CP_PROTECT settings * @pwrup_reglist pwrup reglist for preemption + * @thinmem_config: GMU thinmem configuration */ struct a6xx_info { const struct adreno_reglist *hwcg; @@ -56,6 +57,7 @@ struct a6xx_info { u32 gmu_cgc_mode; u32 prim_fifo_threshold; const struct a6xx_bcm *bcms; + u32 thinmem_config; }; struct a6xx_gpu { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index 186a73c0b99c..e33a2258e0f9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -888,6 +888,27 @@ static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) return 0; } +static int a6xx_hfi_send_thinmem_config(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; + u32 data; + int ret; + + if (!info->thinmem_config) + return 0; + + /* Bits [7:4] contain the thinmem_cfg data. */ + data = FIELD_PREP(GENMASK(7, 4), info->thinmem_config); + + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_THINMEM_CFG, 1, data); + if (ret) + DRM_DEV_ERROR(gmu->dev, "Unable to send THINMEM_CFG (%d)\n", ret); + + return ret; +} + static int a6xx_hfi_send_test(struct a6xx_gmu *gmu) { struct a6xx_hfi_msg_test msg = { 0 }; @@ -993,6 +1014,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state) if (ret) return ret; + ret = a6xx_hfi_send_thinmem_config(gmu); + if (ret) + return ret; + ret = a6xx_hfi_send_core_fw_start(gmu); if (ret) return ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h index e10d32ce93e0..5123349a3de6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -244,6 +244,7 @@ struct a6xx_hfi_msg_feature_ctrl { #define HFI_FEATURE_TDCVS 30 #define HFI_FEATURE_DCE 31 #define HFI_FEATURE_IFF_PCLX 32 +#define HFI_FEATURE_THINMEM_CFG 38 #define HFI_FEATURE_SOFT_RESET 0x10000001 #define HFI_FEATURE_DCVS_PROFILE 0x10000002 #define HFI_FEATURE_FAST_CTX_DESTROY 0x10000003 -- 2.55.0