From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Jordan Crouse <jordan@cosmicpenguin.net>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>
Cc: Akhil P Oommen <akhilpo@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Bhaskar Reddy Valluru <bvalluru@qti.qualcomm.com>
Subject: [PATCH 09/15] drm/msm/a8xx: Add Adreno 845 support
Date: Wed, 23 Sep 2026 15:55:49 +0530 [thread overview]
Message-ID: <20260923-hawi-gpu-v1-9-0c3c79a1a470@oss.qualcomm.com> (raw)
In-Reply-To: <20260923-hawi-gpu-v1-0-0c3c79a1a470@oss.qualcomm.com>
From: Bhaskar Reddy Valluru <bvalluru@qti.qualcomm.com>
Adreno 845 GPU is present in the Maili SoC. It is very similar to Hawi GPU
(A850), except that it doesn't have a MALU unit. Add the necessary
register lists and a catalog entry to support this GPU.
Signed-off-by: Bhaskar Reddy Valluru <bvalluru@qti.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 102 ++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +-
drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 4 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 ++++
4 files changed, 117 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 83c6f257f478..ed77cd40ca5e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -2397,6 +2397,65 @@ static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
};
DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
+static const struct adreno_reglist_pipe a845_nonctxt_regs[] = {
+ { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
+ { REG_A8XX_CP_MULTIDRAW_CNTL, 0x00000001, BIT(PIPE_NONE) },
+ { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x01000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000803, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_5, BIT(28) | BIT(30), BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
+ { REG_A7XX_RB_CCU_DBG_ECO_CNTL, BIT(10) | BIT(9), BIT(PIPE_BR) },
+ { REG_A6XX_RB_DBG_ECO_CNTL, BIT(17), BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0C000000, BIT(PIPE_BR) },
+ { REG_A6XX_RB_RBP_CNTL, BIT(5) | BIT(6), BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
+ { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
+ { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, BIT(0), BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
+ { REG_A6XX_SP_CHICKEN_BITS, BIT(24), BIT(PIPE_NONE) },
+ { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
+ { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
+ { REG_A8XX_SP_CHICKEN_BITS_5, BIT(3), BIT(PIPE_NONE) },
+ { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
+ { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x04000000, BIT(PIPE_NONE) },
+ { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) },
+ { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(1), BIT(PIPE_NONE) },
+ { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
+ { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
+ { REG_A8XX_SP_L0_PERF_TUNE, 0x00000024, BIT(PIPE_NONE) },
+ { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
+ { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
+ { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_DBG_ECO_CNTL_0, BIT(31), BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_HW_DBG_CNTL, 0x01410000, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
+ { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00080020, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VSC_VISIBILITY_FLUSH_CNTL, 0x00080004, BIT(PIPE_NONE) },
+ { },
+};
+
static const struct adreno_reglist_pipe a850_nonctxt_regs[] = {
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
{ REG_A8XX_CP_MULTIDRAW_CNTL, 0x00000001, BIT(PIPE_NONE) },
@@ -2825,6 +2884,49 @@ static const struct adreno_info a8xx_gpus[] = {
{ 242, 1 },
{ 221, 2 },
),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x44041400),
+ .family = ADRENO_8XX_GEN2,
+ .fw = {
+ [ADRENO_FW_SQE] = "gen81100_sqe.fw",
+ [ADRENO_FW_GMU] = "gen81400_gmu.bin",
+ [ADRENO_FW_AQE] = "gen81100_aqe.fw",
+ },
+ .gmem = 12 * SZ_1M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV |
+ ADRENO_QUIRK_PREEMPTION |
+ ADRENO_QUIRK_IFPC,
+ .funcs = &a8xx_gpu_funcs,
+ .a6xx = &(const struct a6xx_info) {
+ .protect = &a850_protect,
+ .nonctxt_reglist = a845_nonctxt_regs,
+ .pwrup_reglist = &a850_pwrup_reglist,
+ .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist,
+ .ifpc_reglist = &a850_ifpc_reglist,
+ .gbif_cx = a850_gbif,
+ .max_slices = 3,
+ .gmu_chipid = 0x80e0000,
+ .thinmem_config = 14,
+ .bcms = (const struct a6xx_bcm[]) {
+ { .name = "SH0", .buswidth = 32 },
+ { .name = "MC0", .buswidth = 4 },
+ {
+ .name = "ACV",
+ .fixed = true,
+ .perfmode = BIT(2),
+ .perfmode_bw = 16500000,
+ },
+ { /* sentinel */ },
+ },
+ },
+ .preempt_record_size = 13564 * SZ_1K,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 0xd8, 0 },
+ { 0x11c, 1 },
+ ),
}, {
.chip_ids = ADRENO_CHIP_IDS(0x44051401),
.family = ADRENO_8XX_GEN2,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index f766e5e4c7b5..662f09bec9d5 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -150,7 +150,7 @@ bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu)
* register to ensure correct GDSC and clock status reporting even
* when the GMU MX domain is powered off
*/
- if (adreno_is_a850(adreno_gpu)) {
+ if (adreno_is_a850_family(adreno_gpu)) {
val = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_GFX_PWR_CLK_STATUS);
return !(val &
@@ -658,7 +658,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
if (!test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status))
return;
- if (adreno_is_a840(adreno_gpu) || adreno_is_a850(adreno_gpu))
+ if (adreno_is_a840(adreno_gpu) || adreno_is_a850_family(adreno_gpu))
bitmask = BIT(30);
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index a5b5e4286e4e..3170ba6ef5a0 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -737,10 +737,10 @@ static int hw_init(struct msm_gpu *gpu)
apriv_mask = A8XX_BR_APRIV_MASK;
/*
- * A850's BV pipe raises a spurious RTWROVF fault interrupt;
+ * A845/A850's BV pipe raises a spurious RTWROVF fault interrupt;
* mask it off to avoid false fault recovery.
*/
- if (adreno_is_a850(adreno_gpu) && pipe_id == PIPE_BV)
+ if (adreno_is_a850_family(adreno_gpu) && pipe_id == PIPE_BV)
int_mask &= ~A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_RTWROVF;
a8xx_aperture_acquire(gpu, pipe_id, &flags);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index f99cf5962344..1b05a4760e02 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -612,11 +612,22 @@ static inline int adreno_is_a840(struct adreno_gpu *gpu)
return gpu->info->chip_ids[0] == 0x44050a01;
}
+static inline int adreno_is_a845(struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x44041400;
+}
+
static inline int adreno_is_a850(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x44051401;
}
+static inline int adreno_is_a850_family(struct adreno_gpu *gpu)
+{
+ return adreno_is_a845(gpu) ||
+ adreno_is_a850(gpu);
+}
+
/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
#define ADRENO_VM_START 0x100000000ULL
u64 adreno_private_vm_size(struct msm_gpu *gpu);
--
2.55.0
next prev parent reply other threads:[~2026-09-23 10:27 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 10:25 [PATCH 00/15] drm/msm: Support for Hawi & Maili GPU Akhil P Oommen
2026-09-23 10:25 ` [PATCH 01/15] drm/msm/a6xx: Honor perfmode_bw threshold on A8x Akhil P Oommen
2026-09-23 11:18 ` Konrad Dybcio
2026-09-23 12:11 ` Dmitry Baryshkov
2026-09-23 10:25 ` [PATCH 02/15] drm/msm/a6xx: Fix secondary rail vote in ARC votes Akhil P Oommen
2026-09-23 10:25 ` [PATCH 03/15] drm/msm/a6xx: Fix RPMH dependency votes Akhil P Oommen
2026-09-23 12:12 ` Dmitry Baryshkov
2026-09-23 10:25 ` [PATCH 04/15] drm/msm/a6xx: Factor out RPMh arc-vote helpers Akhil P Oommen
2026-09-23 10:25 ` [PATCH 05/15] drm/msm/a6xx: Add BX rail support to GMU dependency votes Akhil P Oommen
2026-09-23 10:25 ` [PATCH 06/15] drm/msm/a6xx: Clamp MX dependency vote Akhil P Oommen
2026-09-23 11:19 ` Konrad Dybcio
2026-09-23 10:25 ` [PATCH 07/15] drm/msm/a8xx: Add Adreno 850 support Akhil P Oommen
2026-09-23 10:25 ` [PATCH 08/15] drm/msm/a6xx: Send THINMEM config to GMU for A850 Akhil P Oommen
2026-09-23 10:25 ` Akhil P Oommen [this message]
2026-09-23 10:25 ` [PATCH 10/15] dt-bindings: display/msm: Document A850 GPU and GMU Akhil P Oommen
2026-09-23 13:00 ` Krzysztof Kozlowski
2026-09-25 20:35 ` Akhil P Oommen
2026-09-23 10:25 ` [PATCH 11/15] dt-bindings: display/msm: Document A845 " Akhil P Oommen
2026-09-23 10:25 ` [PATCH 12/15] arm64: dts: qcom: hawi: Add GPU support Akhil P Oommen
2026-09-23 10:25 ` [PATCH 13/15] arm64: dts: qcom: hawi-mtp: Enable GPU Akhil P Oommen
2026-09-23 10:25 ` [PATCH 14/15] arm64: dts: qcom: maili: Add GPU support Akhil P Oommen
2026-09-23 10:25 ` [PATCH 15/15] arm64: dts: qcom: maili-mtp: Enable GPU Akhil P Oommen
2026-09-23 19:24 ` [PATCH 00/15] drm/msm: Support for Hawi & Maili GPU Connor Abbott
2026-09-24 13:41 ` Akhil P Oommen
2026-09-24 14:06 ` Connor Abbott
2026-09-25 19:58 ` Akhil P Oommen
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