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Tue, 22 Sep 2026 18:51:15 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Frank Li , Niklas Cassel , Sherry Sun , Arnd Bergmann , Christian Bruel , Sascha Hauer , Vidya Sagar , Xincheng Zhang , Alex Elder , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Neil Armstrong , Marek Vasut , Inochi Amaoto , Pengpeng Hou , Ping-Ke Shih , Anirudh Srinivasan , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v6 1/6] PCI: spacemit-k1: Add device data support Date: Wed, 23 Sep 2026 09:50:10 +0800 Message-ID: <20260923015016.64069-2-inochiama@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260923015016.64069-1-inochiama@gmail.com> References: <20260923015016.64069-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit To reuse the K1 PCIe driver logic for K3 PCIe controller, add device data to handle the K1 specific logic and make room for the incoming logic for K3. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c index 0564c46e2f48..ab2953ad8f56 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -45,8 +45,17 @@ #define PCIE_CONTROL_LOGIC 0x0004 #define PCIE_SOFT_RESET BIT(0) +struct k1_pcie; + +struct k1_pcie_device_data { + const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ops *ops; + int (*parse_port)(struct k1_pcie *k1); +}; + struct k1_pcie { struct dw_pcie pci; + const struct k1_pcie_device_data *data; struct phy *phy; void __iomem *link; struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ @@ -274,14 +283,21 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) static int k1_pcie_probe(struct platform_device *pdev) { + const struct k1_pcie_device_data *data; struct device *dev = &pdev->dev; struct k1_pcie *k1; int ret; + data = device_get_match_data(dev); + if (!data) + return -ENODATA; + k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); if (!k1) return -ENOMEM; + k1->data = data; + k1->pmu = syscon_regmap_lookup_by_phandle_args(dev_of_node(dev), SYSCON_APMU, 1, &k1->pmu_off); @@ -295,11 +311,11 @@ static int k1_pcie_probe(struct platform_device *pdev) "failed to map \"link\" registers\n"); k1->pci.dev = dev; - k1->pci.ops = &k1_pcie_ops; + k1->pci.ops = data->ops; k1->pci.pp.num_vectors = MAX_MSI_IRQS; dw_pcie_cap_set(&k1->pci, REQ_RES); - k1->pci.pp.ops = &k1_pcie_host_ops; + k1->pci.pp.ops = data->host_ops; /* Hold the PHY in reset until we start the link */ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, @@ -316,7 +332,7 @@ static int k1_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, k1); - ret = k1_pcie_parse_port(k1); + ret = data->parse_port(k1); if (ret) return dev_err_probe(dev, ret, "failed to parse root port\n"); @@ -334,8 +350,14 @@ static void k1_pcie_remove(struct platform_device *pdev) dw_pcie_host_deinit(&k1->pci.pp); } +static const struct k1_pcie_device_data k1_pcie_device_data = { + .host_ops = &k1_pcie_host_ops, + .ops = &k1_pcie_ops, + .parse_port = k1_pcie_parse_port, +}; + static const struct of_device_id k1_pcie_of_match_table[] = { - { .compatible = "spacemit,k1-pcie", }, + { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data }, { } }; MODULE_DEVICE_TABLE(of, k1_pcie_of_match_table); -- 2.55.0