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Tue, 22 Sep 2026 18:51:17 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Frank Li , Niklas Cassel , Sherry Sun , Arnd Bergmann , Christian Bruel , Sascha Hauer , Vidya Sagar , Xincheng Zhang , Alex Elder , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Neil Armstrong , Marek Vasut , Inochi Amaoto , Pengpeng Hou , Ping-Ke Shih , Anirudh Srinivasan , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v6 2/6] PCI: spacemit-k1: Add multiple PHY handles support Date: Wed, 23 Sep 2026 09:50:11 +0800 Message-ID: <20260923015016.64069-3-inochiama@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260923015016.64069-1-inochiama@gmail.com> References: <20260923015016.64069-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The PCIe controller on Spacemit K3 may use multiple PHYs at the same time. The feature is not supported by the current driver. So extend the PHY definition to support multiple PHY handles. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 57 ++++++++++++++----- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c index ab2953ad8f56..8c4f0b09fe24 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -51,12 +51,14 @@ struct k1_pcie_device_data { const struct dw_pcie_host_ops *host_ops; const struct dw_pcie_ops *ops; int (*parse_port)(struct k1_pcie *k1); + unsigned int max_phy_count; }; struct k1_pcie { struct dw_pcie pci; const struct k1_pcie_device_data *data; - struct phy *phy; + struct phy_bulk_data *phys; + unsigned int phy_count; void __iomem *link; struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ u32 pmu_off; @@ -115,6 +117,25 @@ static void k1_pcie_disable_resources(struct k1_pcie *k1) clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); } +static int k1_pcie_get_phy_handle(struct k1_pcie *k1, struct device_node *node) +{ + const struct k1_pcie_device_data *data = k1->data; + struct device *dev = k1->pci.dev; + int count; + + count = devm_of_phy_bulk_get_all(dev, node, &k1->phys); + if (count < 0) + return count; + if (!count) + return -ENOENT; + if (count > data->max_phy_count) + return -EINVAL; + + k1->phy_count = count; + + return 0; +} + /* FIXME: Disable ASPM L1 to avoid errors reported on some NVMe drives */ static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) { @@ -170,12 +191,13 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) */ regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); - ret = phy_init(k1->phy); - if (ret) { - k1_pcie_disable_resources(k1); + ret = phy_bulk_init(k1->phy_count, k1->phys); + if (ret) + goto failed_phy_init; - return ret; - } + ret = phy_bulk_power_on(k1->phy_count, k1->phys); + if (ret) + goto failed_phy_power_on; /* Deassert fundamental reset (drive PERST# high) */ regmap_clear_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST); @@ -184,6 +206,14 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) k1_pcie_disable_aspm_l1(k1); return 0; + +failed_phy_power_on: + phy_bulk_exit(k1->phy_count, k1->phys); +failed_phy_init: + k1_pcie_disable_resources(k1); + + return ret; + } static void k1_pcie_deinit(struct dw_pcie_rp *pp) @@ -195,7 +225,8 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, PCIE_RC_PERST); - phy_exit(k1->phy); + phy_bulk_power_off(k1->phy_count, k1->phys); + phy_bulk_exit(k1->phy_count, k1->phys); k1_pcie_disable_resources(k1); } @@ -262,23 +293,18 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) { struct device *dev = k1->pci.dev; struct device_node *root_port; - struct phy *phy; + int ret; /* We assume only one root port */ root_port = of_get_next_available_child(dev_of_node(dev), NULL); if (!root_port) return -EINVAL; - phy = devm_of_phy_get(dev, root_port, NULL); + ret = k1_pcie_get_phy_handle(k1, root_port); of_node_put(root_port); - if (IS_ERR(phy)) - return PTR_ERR(phy); - - k1->phy = phy; - - return 0; + return ret; } static int k1_pcie_probe(struct platform_device *pdev) @@ -354,6 +380,7 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { .host_ops = &k1_pcie_host_ops, .ops = &k1_pcie_ops, .parse_port = k1_pcie_parse_port, + .max_phy_count = 1, }; static const struct of_device_id k1_pcie_of_match_table[] = { -- 2.55.0