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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:22:57 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Linus Walleij , Rob Herring , Samuel Holland Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller Date: Wed, 23 Sep 2026 21:16:53 +0100 Message-ID: <20260923201701.43391-3-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit One controller at 0x01c20800 with four external interrupt banks. Signed-off-by: Pablo Mazzini --- .../pinctrl/allwinner,sun8i-b288-pinctrl.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml new file mode 100644 index 000000000000..806da97ab708 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun8i-b288-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner B288 Pin Controller + +maintainers: + - Chen-Yu Tsai + - Jernej Skrabec + +properties: + compatible: + const: allwinner,sun8i-b288-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: + One interrupt per bank of external interrupt capable pins. + maxItems: 4 + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + "#gpio-cells": + const: 3 + + "#interrupt-cells": + const: 3 + +patternProperties: + "-pins$": + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml# + additionalProperties: false + + properties: + pins: true + function: true + bias-pull-up: true + bias-pull-down: true + bias-disable: true + drive-strength: + enum: [10, 20, 30, 40] + + required: + - pins + - function + + "^vcc-p[bcdfg]-supply$": + description: + Power supplies for pin banks. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-b288-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + }; + }; -- 2.53.0