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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f9895c1asm10197680c88.12.2026.09.23.23.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 23:10:36 -0700 (PDT) From: Varadarajan Narayanan Date: Thu, 24 Sep 2026 11:40:05 +0530 Subject: [PATCH v3 4/5] phy: qcom: snps-femto-v2: Move PHY init registers to config tables Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260924-phy-v3-4-088e7be0cfaa@oss.qualcomm.com> References: <20260924-phy-v3-0-088e7be0cfaa@oss.qualcomm.com> In-Reply-To: <20260924-phy-v3-0-088e7be0cfaa@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Manu Gautam , Stephen Boyd , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDAyNiBTYWx0ZWRfX0OtcrwbI/Z5x XfnBrD697IF7FO8L1mu1SlIwgIiwTHGeR+4cgqsRHU3HwZVrYvAPZFo2DOABUcnAHqRsNeLhlwA m78Y+5awQkgoQofpdUuIQUloqjIwbxI= X-Proofpoint-ORIG-GUID: Oum81xl-Sk8E1W1aEbeUvbTdwmMj3M7X X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDAyNiBTYWx0ZWRfXyg7HtZAIhHGy to6K6HTsqaiG3pC0iEkEQnZk/2/iJwBxHVi1GHhVB9oGJLRGiDoeyZQTPysQ5OmI1DqwQNvizDC TKFJEoB7qHMh50dRu4GxrQclwfrJGAHuTv62cz2nl4wttdvc11ffiDxV+yxJATmB6ToiDz/ijmd enXmmLVXdegUh1J/sNO+r9jS9MgikRw+OWgHyzh4Ye/uJXwx2IrYw0+f6whzBdG66wR8VCquWOG afX3xUZu2TxPypR9ZPuQx7Gv58tno7ULK3d2j2vZG11Q2cS7Ss38YjueLs/SXpVSvkJRQUqfYnH CBzmbVtjeH+FDClUq1kzkl1Ba5egnco7ouK1VT83nlo9wZomz1OxFaBFK8C+fVNMAspzTfSfBMM FholzLzvI4wMwKrkwRrD3+QVh/mDisCVFYiXLYxXGuW5ns1x7o5rQshCAbGXsEUV1ExshIcWQ70 0kxe8XUVibZ9zhN82Jg== X-Authority-Analysis: v=2.4 cv=a6SlZkSF c=1 sm=1 tr=0 ts=6ab4bede cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=dpbSYRCFOxhwq305YcMA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: Oum81xl-Sk8E1W1aEbeUvbTdwmMj3M7X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240026 The driver currently programs the common PHY register sequence directly in qcom_snps_hsphy_init(), with the fixed register writes split around the override parameter handling. This makes it hard to support SoCs that need a different sequence or different values. Move the fixed pre- and post-override register programming into per- compatible configuration tables, and keep the 7 nm override parameters in the same match-data structure. This allows the driver to share the common sequence while adding SoC-specific sequences for future platforms such as IPQ9650. Additionally, address the register bit field mask & value mixup for USB2_PHY_USB_PHY_REFCLK_CTRL in qcom_snps_hsphy_init() and USB2_AUTO_RESUME in qcom_snps_hsphy_suspend(). Fixes: 51e8114f80d07 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Fixes: 0d75f508a9d56 ("phy: qcom-snps: Add runtime suspend and resume handlers") Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 126 ++++++++++++++++---------- 1 file changed, 79 insertions(+), 47 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 980ad1fb1e2e..b6bbf2b570c7 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -104,6 +104,20 @@ struct phy_override_seq { u8 mask; }; +struct phy_reg_config { + u32 offset; + u32 mask; + u32 val; +}; + +struct phy_config_data { + const struct phy_reg_config *pre_tuning; + const struct override_param_map *override; + const struct phy_reg_config *post_tuning; + const u32 num_pre_tuning; + const u32 num_post_tuning; +}; + #define NUM_HSPHY_TUNING_PARAMS (9) /** @@ -193,7 +207,7 @@ static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy) usleep_range(500, 1000); qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - 0, USB2_AUTO_RESUME); + USB2_AUTO_RESUME, 0); } return 0; @@ -383,13 +397,40 @@ static const struct override_param_map sc7280_snps_7nm_phy[] = { {}, }; +static const struct phy_reg_config hs_5nm_phy_pre_tuning[] = { + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, +}; + +static const struct phy_reg_config hs_5nm_phy_post_tuning[] = { + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0 }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); + const struct phy_config_data *data; + const struct phy_reg_config *tmp; int ret, i; dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); + data = of_device_get_match_data(hsphy->dev); + if (!data) + return -ENODEV; + ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); if (ret) return ret; @@ -414,24 +455,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) goto disable_clks; } - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, POR); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - FSEL_MASK, 0); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - PLLBTUNE, PLLBTUNE); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, - REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, - VBUSVLDEXT0, VBUSVLDEXT0); + for (tmp = data->pre_tuning, i = 0; i < data->num_pre_tuning; i++, tmp++) + qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val); for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) { if (hsphy->update_seq_cfg[i].need_update) @@ -441,28 +466,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) hsphy->update_seq_cfg[i].value); } - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, - VREGBYPASS, VREGBYPASS); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, - SLEEPM, SLEEPM); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - SIDDQ, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + for (tmp = data->post_tuning, i = 0; i < data->num_post_tuning; i++, tmp++) + qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val); hsphy->phy_initialized = true; @@ -495,14 +500,38 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = { .owner = THIS_MODULE, }; +static const struct phy_config_data hs_5nm_phy = { + .pre_tuning = hs_5nm_phy_pre_tuning, + .num_pre_tuning = ARRAY_SIZE(hs_5nm_phy_pre_tuning), + .post_tuning = hs_5nm_phy_post_tuning, + .num_post_tuning = ARRAY_SIZE(hs_5nm_phy_post_tuning), +}; + +static const struct phy_config_data hs_7nm_phy = { + .pre_tuning = hs_5nm_phy_pre_tuning, + .num_pre_tuning = ARRAY_SIZE(hs_5nm_phy_pre_tuning), + .override = sc7280_snps_7nm_phy, + .post_tuning = hs_5nm_phy_post_tuning, + .num_post_tuning = ARRAY_SIZE(hs_5nm_phy_post_tuning), +}; + static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { - { .compatible = "qcom,sm8150-usb-hs-phy", }, - { .compatible = "qcom,usb-snps-hs-5nm-phy", }, + { + .compatible = "qcom,sm8150-usb-hs-phy", + .data = &hs_5nm_phy, + }, + { + .compatible = "qcom,usb-snps-hs-5nm-phy", + .data = &hs_5nm_phy, + }, { .compatible = "qcom,usb-snps-hs-7nm-phy", - .data = &sc7280_snps_7nm_phy, + .data = &hs_7nm_phy, + }, + { + .compatible = "qcom,usb-snps-femto-v2-phy", + .data = &hs_5nm_phy, }, - { .compatible = "qcom,usb-snps-femto-v2-phy", }, { } }; MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); @@ -541,11 +570,14 @@ static void qcom_snps_hsphy_read_override_param_seq(struct device *dev) s32 val; int ret, i; struct qcom_snps_hsphy *hsphy; - const struct override_param_map *cfg = of_device_get_match_data(dev); + const struct phy_config_data *data = of_device_get_match_data(dev); + const struct override_param_map *cfg; - if (!cfg) + if (!data || !data->override) return; + cfg = data->override; + hsphy = dev_get_drvdata(dev); for (i = 0; cfg[i].prop_name != NULL; i++) { -- 2.34.1