Re: [PATCH net-next 1/2] dt-bindings: net: altr,socfpga-stmmac: Add altr,socfpga-stmmac-agilex5-tsn compatible

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: missing agilex5-tsn compatible in allOf constraints
--

commit da393d02e6d50cb4f0bb95604f9b3890a2fc868b
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

dt-bindings: net: altr,socfpga-stmmac: Add altr,socfpga-stmmac-agilex5-tsn compatible
    
The Agilex5 SoCDK TSN Config2 gmac1 path includes an FPGA soft-IP
GMII-to-RGMII converter between the DWXGMAC and the PHY. The converter
provides the RGMII TX/RX delays and presents GMII toward the MAC, unlike
a plain altr,socfpga-stmmac-agilex5 port with no such converter.

> diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> index d8f90d36d2469..ca768937d8905 100644
> --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
[ ... ]
> @@ -42,7 +43,9 @@ properties:
>            - const: snps,dwmac-3.74a
>            - const: snps,dwmac
>        - items:
> -          - const: altr,socfpga-stmmac-agilex5
> +          - enum:
> +              - altr,socfpga-stmmac-agilex5
> +              - altr,socfpga-stmmac-agilex5-tsn
>            - const: snps,dwxgmac-2.10
>  
>    clocks:

[Severity: Medium]
Since this adds a new Agilex5 compatible string, should it also be included
in the allOf conditional block further down in the file?

Currently, the schema in this file enforces Agilex5 constraints:

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: altr,socfpga-stmmac-agilex5
    then:
      properties:
        interrupts:
          minItems: 17
        dma-coherent: true
    else:
      properties:
        interrupts:
          maxItems: 1
        dma-coherent: false

Without adding the new TSN compatible to this if condition, nodes using it
will incorrectly fall into the legacy else branch, restricting them to 1
interrupt and disabling dma-coherent.

Does this new hardware variant share the 17 interrupts and dma-coherent
constraints of the base Agilex5?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923021823.46649-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=1