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Thu, 24 Sep 2026 09:50:10 -0700 (PDT) Received: from dev-ag.figment.co.za ([192.145.132.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a3625ccsm327139f8f.22.2026.09.24.09.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 09:50:09 -0700 (PDT) From: Andrew Gaylard To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, qinjian@cqplus1.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux@armlinux.org.uk, Andrew Gaylard Subject: [PATCH v5 4/6] arm: sunplus: enable SMP via PSCI on SP7021 Date: Thu, 24 Sep 2026 18:49:20 +0200 Message-ID: <20260924164922.117236-5-ag@ffroot.co.za> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260924164922.117236-1-ag@ffroot.co.za> References: <20260924164922.117236-1-ag@ffroot.co.za> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The SP7021 firmware implements PSCI 0.2 via SMC. Add the psci node and enable-method = "psci" on each CPU node to allow the kernel to bring up all four Cortex-A7 cores. Verified by boot log: "psci: SMC Calling Convention v1.0" and "smp: Brought up 1 node, 4 CPUs". Signed-off-by: Andrew Gaylard --- arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi index 493d32357e4e..b73cfde7ace4 100644 --- a/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi @@ -24,27 +24,36 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; clock-frequency = <931000000>; + enable-method = "psci"; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; clock-frequency = <931000000>; + enable-method = "psci"; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; clock-frequency = <931000000>; + enable-method = "psci"; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; clock-frequency = <931000000>; + enable-method = "psci"; }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + gic: interrupt-controller@9f101000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; -- 2.53.0