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Fri, 25 Sep 2026 01:46:50 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Abel Vesa , Abel Vesa , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 3/4] clk: qcom: Add lpass audio clock controller driver for Glymur Date: Fri, 25 Sep 2026 09:46:34 +0100 Message-ID: <20260925084635.112399-4-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260925084635.112399-1-srinivas.kandagatla@oss.qualcomm.com> References: <20260925084635.112399-1-srinivas.kandagatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Y2Winj6PwaAxYS4luj2rFLMED8CXbImm X-Authority-Analysis: v=2.4 cv=QYnzLcbv c=1 sm=1 tr=0 ts=6ab634fd cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=ZsC4DHZuhs/kKio7QBcDoQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=7GdS1con5BCYmhUutoQA:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDAzNCBTYWx0ZWRfXyiZkZKPajyrE bCerxY+k4yeWJC6KqJowS2EHwqf0yVVqXJdlv1oETiK868+spdSE8X0z7HBsodYmPDeD4cg4nEp ErNAPYYckWk6WHZ9uvTT289GjzPECA7JJm8VeoONF/0rNkLtmdk9wPyFJCMgCVmneqiCCp29FVZ Gg25gGN74wvwDiWnQgjlnIU90C70Ux50Calfh25irVGxpXS+xmpaIcoy3slSUtPHSEB0wi1OAMU DmM2YRdfakJy33B+awIcpE9YXym2+viEJT5wdU9qojNWuPeg2v9NfevLlocUeTkGhWWH89J0lEu 7HiZrZTNH8N3OE8fSiv4hV8BTm7VHLge9GyqfEdT5CeYD5GYAc+nOpRDSdXSYo9UHcircQ/TIqI R8x7ZXUsj/xZ6l7BYDuTclmhThEHyV/BJSHJfkZGWUUen7/rB+RRRFDTYi0cSQlPqTym0X/EQ9N b3kUsukVJEjU78e5G8g== X-Proofpoint-ORIG-GUID: Y2Winj6PwaAxYS4luj2rFLMED8CXbImm X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDAzNCBTYWx0ZWRfXxKZ78Vzf1+Tp HcuvbePY5Eoono5mPtHIme9RHEmEvBEe+xVx7vfvNjf5ovgsPO+RBQ/Id2yfTwfW+QuQuMxZaKg mnTEYx/+n56il71bu6F919eYrnhrqI0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250034 Add support for the lpass audio clock controller found on Glymur based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla Reviewed-by: Abel Vesa --- drivers/clk/qcom/Kconfig | 11 +++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-glymur.c | 68 +++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 3bf39a2c54c8..c9f5daed0e14 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1264,6 +1264,17 @@ config SC_LPASSCC_8280XP Say Y if you want to use the LPASS branch clocks of the LPASS clock controller to reset the LPASS subsystem. +config SC_LPASSCC_GLYMUR + tristate "GLYMUR Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST + default m if ARCH_QCOM + help + Support for the LPASS clock controller on Glymur devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. Required for the LPASS + audio macros and the SoundWire compute-mode controller to leave + reset on Glymur. + config SC_LPASS_CORECC_7180 tristate "SC7180 LPASS Core Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index bd70e18a7118..2bad94a1d982 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -150,6 +150,7 @@ obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o +obj-$(CONFIG_SC_LPASSCC_GLYMUR) += lpasscc-glymur.o obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o diff --git a/drivers/clk/qcom/lpasscc-glymur.c b/drivers/clk/qcom/lpasscc-glymur.c new file mode 100644 index 000000000000..356625dce99e --- /dev/null +++ b/drivers/clk/qcom/lpasscc-glymur.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpass_audiocc_glymur_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, + [LPASS_AUDIO_SWR_WSA1_CGCR] = { 0xb0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 }, + [LPASS_AUDIO_SWR_WSA3_CGCR] = { 0x300c, 1 }, + [LPASS_AUDIO_SWR_WSA4_CGCR] = { 0x301c, 1 }, +}; + +static const struct regmap_config lpass_audiocc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-audio-csr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_glymur_reset_desc = { + .config = &lpass_audiocc_glymur_regmap_config, + .resets = lpass_audiocc_glymur_resets, + .num_resets = ARRAY_SIZE(lpass_audiocc_glymur_resets), +}; + +static const struct of_device_id lpasscc_glymur_match_table[] = { + { + .compatible = "qcom,glymur-lpassaudiocc", + .data = &lpass_audiocc_glymur_reset_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpasscc_glymur_match_table); + +static int lpasscc_glymur_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc = device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_glymur_driver = { + .probe = lpasscc_glymur_probe, + .driver = { + .name = "lpasscc-glymur", + .of_match_table = lpasscc_glymur_match_table, + }, +}; + +module_platform_driver(lpasscc_glymur_driver); + +MODULE_AUTHOR("Srinivas Kandagatla "); +MODULE_DESCRIPTION("QTI LPASSCC Glymur Driver"); +MODULE_LICENSE("GPL"); -- 2.53.0