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[79.29.83.136]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49fe5dfa6a7sm266231245e9.12.2026.09.25.11.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 11:24:53 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Matthias Brugger , AngeloGioacchino Del Regno , "Chester A. Unal" , Daniel Golle , Heiner Kallweit , Russell King , Simon Horman , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v23 2/9] dt-bindings: net: Document support for AN8855 Switch Internal PHY Date: Fri, 25 Sep 2026 20:24:24 +0200 Message-ID: <20260925182435.21207-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260925182435.21207-1-ansuelsmth@gmail.com> References: <20260925182435.21207-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document support for AN8855 Switch Internal PHY. Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal PHYs on the MDIO bus. Each PHY might need to be calibrated to correctly work with the use of the eFUSE provided by the Switch SoC. This can be enabled by defining in the PHY node the NVMEM cell properties. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/net/airoha,an8855-phy.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml new file mode 100644 index 000000000000..d2f86116badf --- /dev/null +++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Switch Internal PHY + +maintainers: + - Christian Marangi + +description: > + Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal + PHYs on the MDIO bus. + + Each PHY might need to be calibrated to correctly work with the + use of the eFUSE provided by the Switch SoC. + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-idc0ff.0410 + required: + - compatible + +properties: + reg: + maxItems: 1 + + nvmem-cells: + items: + - description: phandle to SoC eFUSE tx_a + - description: phandle to SoC eFUSE tx_b + - description: phandle to SoC eFUSE tx_c + - description: phandle to SoC eFUSE tx_d + + nvmem-cell-names: + items: + - const: tx_a + - const: tx_b + - const: tx_c + - const: tx_d + +required: + - compatible + - reg + +dependentRequired: + nvmem-cells: [ nvmem-cell-names ] + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + compatible = "ethernet-phy-idc0ff.0410", + "ethernet-phy-ieee802.3-c45"; + + reg = <1>; + }; + + ethernet-phy@2 { + compatible = "ethernet-phy-idc0ff.0410", + "ethernet-phy-ieee802.3-c45"; + + reg = <2>; + + nvmem-cells = <&shift_sel_port0_tx_a>, + <&shift_sel_port0_tx_b>, + <&shift_sel_port0_tx_c>, + <&shift_sel_port0_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + }; -- 2.55.0