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([171.245.4.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df9142bfd4sm25512285ad.52.2026.09.26.19.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2026 19:56:34 -0700 (PDT) From: Nguyen Minh Tien To: Wilken Gottwalt , Bjorn Andersson Cc: Baolin Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Andre Przywara , Bastian Germann , linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, tien.nguyenminh@embeddedlinux.blog Subject: [PATCH 0/3] hwspinlock: sun6i: Allwinner D1 and T113 support Date: Sun, 27 Sep 2026 09:56:23 +0700 Message-Id: <20260927025626.69614-1-tien.nguyenminh@embeddedlinux.blog> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This adds the hardware spinlock of the D1 and T113. The sun6i driver already handles this block, but it looks up its clock and reset by name, which the binding doesn't allow, so a node written to the binding never probes. Patch 1 fixes the driver, as suggested when this came up for the A64 [1]. Patch 3 needs it for the device to probe. Wilken asked then for testing with Crust running [2], as Crust owns part of this block on the SoCs it supports. That doesn't apply here: Crust doesn't run on the D1 or T113, no devicetree in mainline has this node for any other SoC, and patch 1 changes only how the clock and reset are found, not when the driver enables or asserts them. I tested it on a MangoPi MQ-Dual (T113-S3), not only between the two Cortex-A7 cores but also against FreeRTOS on the HiFi4 DSP, the other side this block is there for: - the driver finds 32 locks; - for each lock, while Linux or the DSP held it, the other side was refused, and got it once it was freed; - both A7 cores and the DSP each added 1 to a shared counter a million times under one lock, and the total was exact in every run. Without the lock, over a third of the updates were lost. I have no D1 board to test on. [1] https://lore.kernel.org/f720eaf9-01d0-0e57-f6bf-9aade00aafb8@linaro.org [2] https://lore.kernel.org/20230216095454.54f4d5ca@posteo.net Nguyen Minh Tien (3): hwspinlock: sun6i: Get the clock and the reset without names dt-bindings: hwlock: sun6i: Add compatible for Allwinner D1 riscv: dts: allwinner: d1-t113: Add the hardware spinlock .../bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml | 7 ++++++- arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi | 9 +++++++++ drivers/hwspinlock/sun6i_hwspinlock.c | 4 ++-- 3 files changed, 17 insertions(+), 3 deletions(-) base-commit: 165768bb70265b5c38cf0b73fafd75be235f8b14 -- 2.34.1