Re: [PATCH v2 11/11] ARM: sunxi: add B288 and the PocketBook Verse board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] arm: missing SMP enable-method prevents secondary CPU boot
- [Low] serial: missing pinctrl assignment for uart0
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commit 5bd2057523d9c0e8b398682ab9b915f189883892
Author: Pablo Mazzini <pmazzini@gmail.com>

ARM: sunxi: add B288 and the PocketBook Verse board

This commit introduces device tree support for the Allwinner B288 SoC and
the PocketBook Verse board. It configures the CPU, timers, and basic
peripherals like MMC, I2C, and UART.

> diff --git a/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts b/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts
> new file mode 100644
> index 0000000000000..91c89d5a097e6
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts

[ ... ]

> +&uart0 {
> +	status = "okay";
> +};

[Severity: Low]
Is the pin control configuration missing here? The uart0 node is enabled, but
it lacks the pinctrl-names and pinctrl-0 properties. 

There is a uart0_pb_pins group defined in sun8i-b288.dtsi, but it appears to be
unreferenced. Without explicit pinctrl properties, the kernel might rely on the
bootloader's initial pin state, which could lead to a broken serial console
after suspend/resume cycles.

[ ... ]

> diff --git a/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi b/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi
> new file mode 100644
> index 0000000000000..f5feec87defcc
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi

[ ... ]

> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-names = "cpu";
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <1>;
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-names = "cpu";
> +		};
> +	};

[Severity: Medium]
Does the cpus block or the cpu1 node need an enable-method property to
properly bring up the secondary core? 

Because this board uses Allwinner's boot0 rather than PSCI, the kernel's
smp_init() sequence may not have the necessary operations to wake this
secondary core if a custom enable-method isn't defined, which would result in
the loss of SMP functionality.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260927151016.186493-1-pmazzini@gmail.com?part=11