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This IPC needs shared memory buffers. Reserve memory to facilitate this IPC. In addition TI MCU R5 firmware also uses MCU SRAM, hence make this SRAM accessible to R5 remote proc for image loading. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Signed-off-by: Sai Sree Kartheek Adivi --- arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi index 5d7f701420e2d..7084d85665f4d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi @@ -6,6 +6,12 @@ */ &reserved_memory { + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b800000 0x00 0x100000>; @@ -54,6 +60,7 @@ &mcu_r5fss0 { }; &mcu_r5fss0_core0 { + sram = <&mcu_ram>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; -- 2.54.0