Re: [PATCH v9 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: qcom: missing .is_enabled in gate clock ops causes power leak
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commit cd2f6ce18faa02e554ea7e8ca64e0b68dfbbbc9a
Author: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>

clk: qcom: Add LPASS VA CSR heartbeat pulse clock

This commit adds the LPASS VA CSR driver to model the rate generator as
a clock provider. It allows consumers to enable and disable it through
the common clock framework and attaches the DT vote clocks to runtime PM.

> diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c
> new file mode 100644
> index 0000000000000..93eafb2e043ab
> --- /dev/null
> +++ b/drivers/clk/qcom/lpass-va-csr.c
[ ... ]
> +static const struct clk_ops lpass_va_csr_hb_ops = {
> +	.prepare = lpass_va_csr_hb_prepare,
> +	.unprepare = lpass_va_csr_hb_unprepare,
> +	.enable = clk_enable_regmap,
> +	.disable = clk_disable_regmap,
> +};

[Severity: Medium]
Is the .is_enabled callback missing from lpass_va_csr_hb_ops?

The Common Clock Framework explicitly requires the .is_enabled callback for
gate clocks to accurately read the initial hardware state (as documented in
clk_core_is_enabled()). Without this callback, CCF falls back to the software
enable_count, which is 0 at boot.

If the bootloader or previous firmware left the LPASS rate generator enabled,
clk_disable_unused() will assume it is already disabled and skip it, leading
to a persistent power leak.

Could .is_enabled = clk_is_enabled_regmap be added here to ensure the unused
clock can be properly evaluated and disabled?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260928-master-v9-0-2277f09f9a09@oss.qualcomm.com?part=2