Re: [PATCH v5 2/5] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: missing required phys properties in usb3b and usb3c nodes
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commit 89b216baa5d6be0e4a7be800d568bba679087495
Author: Aurelien Jarno <aurelien@aurel32.net>

riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board

This commit adds the USB3 controller nodes (B and C) to the SpacemiT K3 SoC
device tree. It also enables them and adds the corresponding USB2 PHY nodes
for the Pico-ITX board.

> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index 1af47b7f1c8af..cf1c8b572c86b 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi

[ ... ]

> @@ -441,6 +441,66 @@ soc: soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		usb3b: usb@81400000 {
> +			compatible = "spacemit,k3-dwc3";
> +			reg = <0x0 0x81400000 0x0 0x10000>;
> +			interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;

[Severity: Low]
Does omitting the phys and phy-names properties here cause a devicetree
validation regression?

The SoC devicetree fails dtbs_check validation against the binding schema
(spacemit,k1-dwc3.yaml), which unconditionally requires the phys and
phy-names properties.

Should this node define its hardwired connection to usb3b_u2phy via the
phys and phy-names properties here, instead of omitting these SoC-internal
hardwired connections from k3.dtsi and forcing downstream boards to
redundantly define the SoC hardware topology?

> +			interrupt-parent = <&saplic>;
> +			clocks = <&syscon_apmu CLK_APMU_USB3_PORTB_BUS>;

[ ... ]

> +		usb3c: usb@81700000 {
> +			compatible = "spacemit,k3-dwc3";
> +			reg = <0x0 0x81700000 0x0 0x10000>;
> +			interrupts = <148 IRQ_TYPE_LEVEL_HIGH>;

[Severity: Low]
Similarly, does this node also need to define its hardwired connection to
usb3c_u2phy via the phys and phy-names properties to avoid the same schema
validation regression?

> +			interrupt-parent = <&saplic>;
> +			clocks = <&syscon_apmu CLK_APMU_USB3_PORTC_BUS>;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260928205012.3689405-1-aurelien@aurel32.net?part=2