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Peripherals included in this initial set: - Single Cortex-A7 CPU with PSCI idle states - RPMh RSC with clock controller, power domains, and BCM voter - GCC (Global Clock Controller) - TLMM pin controller (110 GPIOs) - Interconnect (aggre-noc, cnoc-main) - GENI UART console (QUP SE3) - SMEM, hardware spinlocks (TCSR mutex) Reviewed-by: Dmitry Baryshkov Reviewed-by: Linus Walleij Reviewed-by: Abel Vesa Signed-off-by: Hardeep Sharma --- This series adds initial support for the Qualcomm Kuno SoC and the Kuno IDP reference board. Kuno is a 32-bit ARM (Cortex-A7) Qualcomm platform. The rest of the series (bindings, GCC, RPMh clocks and power domains, interconnect, pinctrl, geni-se) has been applied and is in linux-next, so v6 carries only the SoC and IDP board devicetree. --- Changes in v6: - Rebased on next-20260928. The rest of the series has been applied, so only the devicetree patch remains. - Addressed v5 review feedback: - Added the full qcom,pdc-ranges map (22 ranges instead of 3), so that all PDC-routed wakeup GPIOs can wake the system. - Added wakeup-parent = <&pdc> to the TLMM node. - Replaced the explicit soc ranges with an empty ranges and named the node soc, matching the other 32-bit Qualcomm SoCs. - Widened the QUP wrapper ranges to cover the whole 32-bit address space instead of a 16 MiB window. - Link to v5: https://lore.kernel.org/all/20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com/ Changes in v5: - Selected QCOM_GDSC from the Kuno GCC config. The driver registers GDSCs (added in v4), so like the other Qualcomm GCC drivers it must select QCOM_GDSC; otherwise, in a configuration where nothing else enables it (e.g. COMPILE_TEST or a minimal Kuno-only build), gdsc_register() returns -ENOSYS and the clock controller fails to probe. - Link to v4: https://lore.kernel.org/all/20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com/ Changes in v4: - Addressed v3 review feedback: - Registered the interconnect NoC provider from an explicit core_initcall() instead of module_platform_driver(), matching the established qcom interconnect driver convention. - Replaced the NA mux-slot placeholder with _ across the pinctrl PINGROUP table, matching the upstream qcom pinctrl convention. - Added minItems: 1 to the interconnect binding clocks property so a single clock is valid (system-noc), and aligned the binding examples with the sdx75 labelled-node style. - Added GDSC power-domain support to the Kuno GCC: the binding now defines GDSC macros and the driver registers the EMAC0, PCIe and USB20 GDSCs, so #power-domain-cells has real backing providers. - Split the cpu-idle-states phandle list so each phandle is on its own line. - Collected Acked-by / Reviewed-by tags from v3. - Link to v3: https://lore.kernel.org/all/20260821-kuno-soc-support-v3-0-196e2b306368@oss.qualcomm.com/ Changes in v3: - Addressed v2 review feedback: - Reworked the interconnect binding clocks: dropped clock-names and replaced the flexible min/maxItems list with fixed per-compatible clocks (aggre-noc: 2, system-noc: 1), required where present and disallowed otherwise, matching the sdx75/glymur shape. - Made #power-domain-cells required on the Kuno GCC binding and declared it on the SoC gcc node, since the Kuno GCC hosts GDSCs and is a power-domain provider (following qcom,sdx75-gcc); the driver's GDSC support will follow separately. - Made the GPIO65/66 QDSS CTI trig1 funcsel-3 route selectable: added a distinct qdss_cti_trig1_mire pin function (and allowed it in the TLMM binding enum), as the duplicate funcsel-2/3 entry left funcsel-3 unreachable. - Collected Acked-by / Reviewed-by tags from v2. - Link to v2: https://lore.kernel.org/all/20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com/ Changes in v2: - Addressed v1 review feedback: - Reworked soc: qcom: geni-se commit message; dropped the Fixes: tag. - Reworded dt-bindings commit messages to the "Document X for the Qualcomm Kuno SoC" one-liner form. - Canonicalized copyright headers on interconnect binding / driver / NoC ID header to the single-line Qualcomm Technologies form. - Dropped unused from the interconnect driver. - Fixed MODULE_DESCRIPTION casing "KUNO" -> "Kuno" in the interconnect driver. - Extended interconnect binding to optionally allow up to four QoS AHB clocks (matches sdx75/glymur shape). - Cleaned up brace/space style in gcc-kuno.c to match peer clock drivers. - Reworked initial DTS: moved idle-states / domain-idle-states inside cpus{}, wrapped fixed clocks in a clocks{} container with peer node names (xo-board, sleep-clk), dropped the pcie_pipe_clk fixed-clock stub (the GCC 4th clock now uses <0> in DTS to match the sdx75 idiom; the YAML example uses a named placeholder), dropped the RPMHPD_CX power-domain reference on GCC (Kuno GCC has no GDSCs / no corner votes / no pm_runtime, so the reference was inert), and added a bootloader hand-off comment on the memory node. - Collected Acked-by / Reviewed-by tags from v1. - Link to v1: https://lore.kernel.org/all/20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com/ --- arch/arm/boot/dts/qcom/Makefile | 1 + arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 ++ arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 444 +++++++++++++++++++++++++++++++ 3 files changed, 470 insertions(+) diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 026d5b682b2b..7327a7b8180e 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ + qcom-kuno-idp.dtb \ qcom-msm8226-microsoft-dempsey.dtb \ qcom-msm8226-microsoft-makepeace.dtb \ qcom-msm8226-microsoft-moneypenny.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts b/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts new file mode 100644 index 000000000000..c2f6650d3fe6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-kuno-idp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "qcom-kuno.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kuno IDP"; + compatible = "qcom,kuno-idp", "qcom,kuno"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-kuno.dtsi b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi new file mode 100644 index 000000000000..82bb4c20dc34 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-kuno.dtsi @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + }; + + idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "standalone-pc"; + entry-latency-us = <350>; + exit-latency-us = <450>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cx-min"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x40000008>; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-kuno", "qcom,scm"; + }; + }; + + memory { + device_type = "memory"; + /* Bootloader will fill base and size */ + reg = <0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_0>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + quickboot@82100000 { + reg = <0x82100000 0x100000>; + no-map; + }; + + aop-image@82200000 { + reg = <0x82200000 0x20000>; + no-map; + }; + + aop-cmd-db@82220000 { + compatible = "qcom,cmd-db"; + reg = <0x82220000 0x20000>; + no-map; + }; + + aop-config@82240000 { + reg = <0x82240000 0x20000>; + no-map; + }; + + uefi-log@82260000 { + reg = <0x82260000 0x10000>; + no-map; + }; + + ipa-fw@82270000 { + reg = <0x82270000 0x10000>; + no-map; + }; + + smem@82280000 { + compatible = "qcom,smem"; + reg = <0x82280000 0xc0000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + tme-crashdump@82340000 { + reg = <0x82340000 0x40000>; + no-map; + }; + + tme-log@82380000 { + reg = <0x82380000 0x4000>; + no-map; + }; + + access-control-db@82384000 { + reg = <0x82384000 0x40000>; + no-map; + }; + + secdata@823c4000 { + reg = <0x823c4000 0x1000>; + no-map; + }; + + modem-efs@823c5000 { + reg = <0x823c5000 0x10000>; + no-map; + }; + + cpucp-fw@82400000 { + reg = <0x82400000 0x80000>; + no-map; + }; + + xbl-dt-log@824c0000 { + reg = <0x824c0000 0x20000>; + no-map; + }; + + qtee@82500000 { + reg = <0x82500000 0x180000>; + no-map; + }; + + trusted-apps@82680000 { + reg = <0x82680000 0x600000>; + no-map; + }; + + mpss-audio@82e00000 { + reg = <0x82e00000 0x5a00000>; + no-map; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gcc: clock-controller@80000 { + compatible = "qcom,kuno-gcc"; + reg = <0x00080000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qup0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x009c0000 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x1 0x0>; + + uart3: serial@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&uart_console_active>; + pinctrl-1 = <&uart_console_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1580000 { + compatible = "qcom,kuno-cnoc-main"; + reg = <0x01580000 0x19200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@1640000 { + compatible = "qcom,kuno-aggre-noc"; + reg = <0x01640000 0x33400>; + clocks = <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,kuno-pdc", "qcom,pdc"; + reg = <0x0b220000 0x10000>; + qcom,pdc-ranges = <1 148 6>, + <9 156 2>, + <17 164 7>, + <26 173 1>, + <29 176 1>, + <40 187 1>, + <46 193 6>, + <52 266 32>, + <84 249 1>, + <85 256 1>, + <86 315 4>, + <90 43 1>, + <91 45 1>, + <92 154 2>, + <94 158 6>, + <100 171 2>, + <102 174 1>, + <103 23 7>, + <110 147 1>, + <111 31 4>, + <115 175 1>, + <116 177 10>, + <126 188 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,kuno-tlmm"; + reg = <0x0f000000 0x400000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 110>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + uart_console_active: uart-console-active-state { + pins = "gpio8", "gpio9"; + function = "qup0_se3_mira"; + drive-strength = <2>; + bias-disable; + }; + + uart_console_sleep: uart-console-sleep-state { + pins = "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + intc: interrupt-controller@17000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x17000000 0x1000>, + <0x17002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@17020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x17020000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@17021000 { + reg = <0x17021000 0x1000>, + <0x17022000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + }; + + apps_rsc: rsc@17040000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x17040000 0x10000>, + <0x17050000 0x10000>, + <0x17060000 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = , + /* drv-1: placeholder (unused) */ + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + power-domains = <&cluster_pd>; + + rpmhcc: clock-controller { + compatible = "qcom,kuno-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,kuno-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; +}; --- base-commit: 6375e61c01e93e35ee7acd336a689ac1fae4b509 change-id: 20260809-kuno-soc-support-1dab826de0bf Best regards, -- Hardeep Sharma