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DDR PHY tuning must not be attempted for such operations; non-PHY DDR usage is unaffected. [0] Add CQSPI_NO_PHY_TUNING_WITH_ODDR_2B_ADDR quirk and check it in cqspi_am654_ospi_execute_tuning(). When the erratum applies, return 0 with read_op->max_freq cleared -- the op-skip signal that tells the caller to try another op variant. [0] https://www.ti.com/lit/er/sprz544c/sprz544c.pdf Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 46 ++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index e21164419b00..6ac3607df0bb 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -37,19 +37,20 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX); /* Quirks */ -#define CQSPI_NEEDS_WR_DELAY BIT(0) -#define CQSPI_DISABLE_DAC_MODE BIT(1) -#define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) -#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) -#define CQSPI_SLOW_SRAM BIT(4) -#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) -#define CQSPI_RD_NO_IRQ BIT(6) -#define CQSPI_DMA_SET_MASK BIT(7) -#define CQSPI_SUPPORT_DEVICE_RESET BIT(8) -#define CQSPI_DISABLE_STIG_MODE BIT(9) -#define CQSPI_DISABLE_RUNTIME_PM BIT(10) -#define CQSPI_NO_INDIRECT_MODE BIT(11) -#define CQSPI_HAS_WR_PROTECT BIT(12) +#define CQSPI_NEEDS_WR_DELAY BIT(0) +#define CQSPI_DISABLE_DAC_MODE BIT(1) +#define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) +#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) +#define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) +#define CQSPI_RD_NO_IRQ BIT(6) +#define CQSPI_DMA_SET_MASK BIT(7) +#define CQSPI_SUPPORT_DEVICE_RESET BIT(8) +#define CQSPI_DISABLE_STIG_MODE BIT(9) +#define CQSPI_DISABLE_RUNTIME_PM BIT(10) +#define CQSPI_NO_INDIRECT_MODE BIT(11) +#define CQSPI_HAS_WR_PROTECT BIT(12) +#define CQSPI_NO_PHY_TUNING_WITH_ODDR_2B_ADDR BIT(13) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -3179,6 +3180,8 @@ static int cqspi_am654_ospi_execute_tuning(struct spi_mem *mem, spi_controller_get_devdata(mem->spi->controller); struct cqspi_flash_pdata *f_pdata; struct device *dev = &cqspi->pdev->dev; + bool op_is_dtr = read_op->cmd.dtr || read_op->addr.dtr || + read_op->dummy.dtr || read_op->data.dtr; int ret = 0; f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; @@ -3194,6 +3197,18 @@ static int cqspi_am654_ospi_execute_tuning(struct spi_mem *mem, return -EOPNOTSUPP; } + /* + * Erratum i2383: in PHY DDR mode, a 2-byte column address locks up + * the address phase. Skip DDR PHY tuning for such operations. + */ + if ((cqspi->ddata->quirks & CQSPI_NO_PHY_TUNING_WITH_ODDR_2B_ADDR) && + read_op->addr.nbytes == 2 && op_is_dtr) { + dev_dbg(dev, + "i2383: skipping DDR PHY tuning (2-byte address)\n"); + read_op->max_freq = 0; + return 0; + } + if (write_op) { /* * For NAND: write the calibration pattern to the page cache. @@ -3236,8 +3251,7 @@ static int cqspi_am654_ospi_execute_tuning(struct spi_mem *mem, f_pdata->phy_read_op.max_freq = mem->spi->post_config_max_speed_hz; - if (read_op->cmd.dtr || read_op->addr.dtr || read_op->dummy.dtr || - read_op->data.dtr) { + if (op_is_dtr) { f_pdata->use_dqs = true; cqspi_phy_pre_config(cqspi, f_pdata, false); ret = cqspi_phy_tuning_ddr(f_pdata, mem); @@ -3835,7 +3849,7 @@ static const struct cqspi_driver_platdata k2g_qspi = { static const struct cqspi_driver_platdata am654_ospi = { .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, - .quirks = CQSPI_NEEDS_WR_DELAY, + .quirks = CQSPI_NEEDS_WR_DELAY | CQSPI_NO_PHY_TUNING_WITH_ODDR_2B_ADDR, .execute_tuning = cqspi_am654_ospi_execute_tuning, }; -- 2.34.1