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[90.154.213.116]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2b0f2f4f53sm531974466b.47.2026.09.29.06.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 06:38:46 -0700 (PDT) Date: Tue, 29 Sep 2026 16:38:44 +0300 From: Petko Manolov To: Dinh Nguyen Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, arnemaximilian.richter@draeger.com, martynas.grybauskas@draeger.com Subject: Re: [PATCH v7 3/3] arm: dts: altera: add Draeger M48 CPU Module Message-ID: <20260929133844.GF10296@carbon.k.g> References: <20260921090735.3174292-1-petko.manolov@konsulko.com> <20260921090735.3174292-4-petko.manolov@konsulko.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On 26-09-28 09:18:03, Dinh Nguyen wrote: > > According to all my documentations, the Cyclone5 SoCFPGA has 3 GPIO ports, and > those are already mapped in the DTSI. The address space that you have > specified here is for FPGA bridge. Which leads me to believe that this GPIO is > in the FPGA. You are correct. These bindigs are some sort of leftover and Draeger folks confirmed that they should be removed. Sending out new patch series... Petko