From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46DD543499F for ; Tue, 29 Sep 2026 13:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790690027; cv=none; b=unhgZilLeiMK3XSxHYPRxZUG/Li4X3wuxQ4x82NC67LlUwkxu5m4SG4+v0s9qAPRKiKXBe5oXG4IYwXkQo/U/Jogz2PVMHYD2tXMkp4+Biz2WVFuZez91lvnxCzvdacviDiDUQ87U9egKmfjVb5QMQ2RrhP4AFQwvv06sZOMsf8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790690027; c=relaxed/simple; bh=XXUYzSLQuTG+pi/k3cgU7pW3WjuBhG2Hx5O4jz9PVfE=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=OcJp+M8AaPqJwNcjvnpIoSfUcl+FnY9pHyVK2nj/rkReIvKa3WdkyHUXJLWAMVT+tkwRmIN4EE9PkUdmQiSST0oRSoOD78pMqzNnPgDzUy06pCTBfPqbcHUiN+EZBR/AoU1qKhoXgL1wNS2wTadUEpAdJ6rywcZQTKTD79Wxuio= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eCfCqqQ6; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eCfCqqQ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94A841F00893; Tue, 29 Sep 2026 13:53:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790690025; bh=6V4/zpJ3TX3nfNscb5ghRNCIIRqZKCOSFyXx0hwxAxw=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=eCfCqqQ6LglNBFfutVZtFLNeopL//V/fTFXI6xVmVB1YCryxmS1If046dG+q9qPO4 PNGEHe+JItDGStQRzBZBNXelxLOHCnhBl8AzlvGrygIkNbrpemlF1ZfPk3gNni2Uz+ H+WnEZIkLCbsYMgFP4Tevza3th6Bm7zoozRqeV/YqQIKbpd51uTR2NM9ccszAE2Fs4 VvYDgjB/qeVlENM3Ry15qmfZfM3SOgHIYGbR6UjqnJwH3T/kxotpOdPsoLNAcsFuQS 7UASwasp0GAo4J8wApwNZciQX1CTUuH47zilVdTzbydp9wiKfIoPZicYBLyd6Y+OhK Tba6PqtMLOmzA== From: sashiko-bot@kernel.org Subject: Re: [PATCH v8 3/3] arm: dts: altera: add Draeger M48 CPU Module Reply-To: sashiko-reviews@lists.linux.dev To: "Petko Manolov" Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org In-Reply-To: <20260929134058.819371-4-petko.manolov@konsulko.com> References: <20260929134058.819371-1-petko.manolov@konsulko.com> <20260929134058.819371-4-petko.manolov@konsulko.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Tue, 29 Sep 2026 13:53:45 +0000 Message-Id: <20260929135345.94A841F00893@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [Low] dts: unnecessary address/size cells in flash leaf node - [Low] dts: deprecated name property in memory node - [Low] dts: deprecated placement of PHY skew properties in MAC node - [Low] dts: typo in aliases node comment -- commit b96c17a8d8e5c99eb2bdb2439e91d0063679636c Author: Petko Manolov arm: dts: altera: add Draeger M48 CPU Module This commit introduces device tree support for the Altera SoCFPGA Cyclone 5 component of the heterogeneous Draeger M48 CPU module. The board boots independently via QSPI and monitors a companion i.MX6 processor. > diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48= .dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts > new file mode 100644 > index 0000000000000..85daa839c3147 > --- /dev/null > +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts > @@ -0,0 +1,91 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com > + */ > +#include "socfpga_cyclone5.dtsi" > + > +/ { > + model =3D "Draeger M48 Cyclone V SoC"; > + compatible =3D "draeger,socfpga-m48", "altr,socfpga-cyclone5", "altr,so= cfpga"; > + > + chosen { > + stdout-path =3D "serial0:115200n8"; > + }; > + > + memory@0 { > + name =3D "memory"; [Severity: Low] Is this name property intended? Explicit use of the name property in the memory node is deprecated by the Devicetree Specification as it is automatically generated by DTC. Leaving it here generates a name_properties DTC warning. > + device_type =3D "memory"; > + reg =3D <0x0 0x40000000>; > + }; > + > + aliases { > + /* this allow the ethaddr uboot environmnet variable contents [Severity: Low] This isn't a bug, but there's a typo in this comment. The word "environmnet" should be "environment". > + * to be added to the gmac0 device tree blob. > + */ > + ethernet0 =3D &gmac0; > + }; > +}; > + > +&gmac0 { > + status =3D "okay"; > + phy-mode =3D "rgmii-id"; > + rxc-skew-ps =3D <1860>; > + rxd0-skew-ps =3D <0>; [Severity: Low] Are these PHY-specific skew properties attached to the correct node? Placing them directly in the &gmac0 MAC node relies on a deprecated driver fallback mechanism (documented in drivers/net/phy/micrel.c). They should normally be attached to a dedicated mdio PHY sub-node. > + rxd1-skew-ps =3D <0>; > + rxd2-skew-ps =3D <0>; > + rxd3-skew-ps =3D <0>; > + rxdv-skew-ps =3D <0>; > + txc-skew-ps =3D <900>; > + txd0-skew-ps =3D <0>; > + txd1-skew-ps =3D <0>; > + txd2-skew-ps =3D <0>; > + txd3-skew-ps =3D <0>; > + txen-skew-ps =3D <0>; > +}; [ ... ] > +&qspi { > + status =3D "okay"; > + > + flash: flash@0 { > + #address-cells =3D <1>; > + #size-cells =3D <1>; [Severity: Low] Are these cells necessary? The flash@0 node lacks child partitions, leaving these properties dangling and triggering an avoid_unnecessary_addr_size DTC warning during compilation. > + compatible =3D "micron,n25q256a", "jedec,spi-nor"; > + reg =3D <0>; --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260929134058.8193= 71-1-petko.manolov@konsulko.com?part=3D3