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Wed, 30 Sep 2026 01:14:02 -0500 From: Colin Huang Date: Wed, 30 Sep 2026 14:10:17 +0800 Subject: [PATCH v9 09/15] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260930-anacapa-devlop-phase-devicetree-v9-9-f08aa0d7182d@gmail.com> References: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> In-Reply-To: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Ryan Chen , Billy Tsai CC: , , , , , Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790748641; l=3698; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=8kEAvGR4wHD+buKRoFqsooBUH7WFB3+NHrtadmWVUT0=; b=2c3HR+pBxx+/kYY9AEv5W7vieikGLEJmTk/SKV8LmxjSAyomf4zuqveWQhLtqF6IvGZFgdAce 7g408LhQ4SDB34VUseNQ6+Jve1ZH5TaTn802aoZOZ12W4zYZqJaR0R/ X-Developer-Key: i=u8813345@gmail.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P1Dnt3hNWewIwYyX5ALpoOXFaaFwnGBFj6BW6uxG3O8sTVrLenau1H+z/zPLUTW9IQzDAqxryWzHK8L0Dc7/5BWNSUnnEtHfMFhZRhdLsU4qxC6xXrLv1qiKhZ6ISrZSERL9SiMfGB+1KfhCeMHFnGhtXZYO9TNA4mKcL0uGd/NlQ8jHoWnooZY6hMPbVcXcb2wXw8q2w5cBPOndAnuO+ZZ5+GYvBCWITN9lDWrc4PX1mJ2Ll83qTBUuGPri/DBDHSFgxVhQSPLz3IJUx4sXx4ZOrY+nv+6/CU5f2kLt+sQa0t7+WzqSV6K+cjjWlcUfJ3g4WHF/Om/LDpbNpsWTY43Fd63825sjGjCMpuKFbv1QXpUGV11PGDWgnlMgGLuj0Cu2mAZtLhvtXL9BCR1M2sWLeIzAG6khN7cs86IIRKJj7zzZaeqCItlPgYWSo5ev X-OriginatorOrg: amdcloud.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 06:14:06.0126 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b43921ac-4022-4dd8-c0c5-08df1eba0837 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A7FF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9551 From: Rex Fu Add PCA9554 GPIO expanders for PDB fuse monitor signals on the Anacapa DVT board. The patch adds GPIO expander definitions for both the left and right PDBs under the i2c8 multiplexer and updates the associated gpio-line-names to reflect the final signal assignments. Signed-off-by: Rex Fu --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 0509bc8bb9cd..2fd7e46daa63 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -2,6 +2,98 @@ #include "aspeed-bmc-facebook-anacapa-evt2.dtsi" +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@22 { + gpio-line-names = + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + i2c@1 { + gpio@22 { + gpio-line-names = + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + + gpio@24 { + gpio-line-names = + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; +}; + &sgpiom0 { gpio-line-names = /*in - out */ -- 2.34.1