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Wed, 30 Sep 2026 06:29:02 +0000 From: "Peng Fan (OSS)" Date: Wed, 30 Sep 2026 14:26:11 +0800 Subject: [PATCH v2 3/3] arm64: dts: imx95: convert eDMA to per-channel child nodes Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260930-edma-iommu-v2-3-72a62bf44c74@nxp.com> References: <20260930-edma-iommu-v2-0-72a62bf44c74@nxp.com> In-Reply-To: <20260930-edma-iommu-v2-0-72a62bf44c74@nxp.com> To: Frank Li , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Frank Li , Joy Zou , imx@lists.linux.dev, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan X-Mailer: b4 0.15.2 X-ClientProxiedBy: SG2P153CA0011.APCP153.PROD.OUTLOOK.COM (2603:1096::21) To AM8PR04MB7874.eurprd04.prod.outlook.com (2603:10a6:20b:24d::9) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM8PR04MB7874:EE_|DU2PR04MB9081:EE_ X-MS-Office365-Filtering-Correlation-Id: 610acf57-63f6-4bdb-3495-08df1ebc1e89 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|19092799006|366016|7416014|376014|1800799024|23010399003|11063799006|56012099006|10067099003|22082099003|18002099003; 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Each child carries its own reg (real per-channel MMIO region) and interrupts property. edma2 (64 channels at 0x42000000): - Channel N at 0x42010000 + N * 0x8000 (size 0x8000) - Paired interrupts: SPI 128-159, two channels per SPI edma3 (64 channels at 0x42210000): - Channel N at 0x42220000 + N * 0x8000 (size 0x8000) - Paired interrupts: SPI 256-287, two channels per SPI edma1 (imx93-edma3, 31 channels with 1:1 non-paired interrupts) is left unchanged as it uses a different interrupt scheme. Assisted-by: LLM Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95.dtsi | 774 ++++++++++++++++++++++++++----- 1 file changed, 646 insertions(+), 128 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index d20c2498b9aa..64570703ce6c 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -635,148 +635,666 @@ edma2: dma-controller@42000000 { compatible = "fsl,imx95-edma5"; reg = <0x42000000 0x210000>; #dma-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; dma-channels = <64>; /* channels 0 and 1 reserved for V2X fast hash */ dma-channel-mask = <0x3>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "dma"; + + dma-channel@42010000 { + reg = <0x42010000 0x8000>; + interrupts = ; + }; + + dma-channel@42018000 { + reg = <0x42018000 0x8000>; + interrupts = ; + }; + + dma-channel@42020000 { + reg = <0x42020000 0x8000>; + interrupts = ; + }; + + dma-channel@42028000 { + reg = <0x42028000 0x8000>; + interrupts = ; + }; + + dma-channel@42030000 { + reg = <0x42030000 0x8000>; + interrupts = ; + }; + + dma-channel@42038000 { + reg = <0x42038000 0x8000>; + interrupts = ; + }; + + dma-channel@42040000 { + reg = <0x42040000 0x8000>; + interrupts = ; + }; + + dma-channel@42048000 { + reg = <0x42048000 0x8000>; + interrupts = ; + }; + + dma-channel@42050000 { + reg = <0x42050000 0x8000>; + interrupts = ; + }; + + dma-channel@42058000 { + reg = <0x42058000 0x8000>; + interrupts = ; + }; + + dma-channel@42060000 { + reg = <0x42060000 0x8000>; + interrupts = ; + }; + + dma-channel@42068000 { + reg = <0x42068000 0x8000>; + interrupts = ; + }; + + dma-channel@42070000 { + reg = <0x42070000 0x8000>; + interrupts = ; + }; + + dma-channel@42078000 { + reg = <0x42078000 0x8000>; + interrupts = ; + }; + + dma-channel@42080000 { + reg = <0x42080000 0x8000>; + interrupts = ; + }; + + dma-channel@42088000 { + reg = <0x42088000 0x8000>; + interrupts = ; + }; + + dma-channel@42090000 { + reg = <0x42090000 0x8000>; + interrupts = ; + }; + + dma-channel@42098000 { + reg = <0x42098000 0x8000>; + interrupts = ; + }; + + dma-channel@420a0000 { + reg = <0x420a0000 0x8000>; + interrupts = ; + }; + + dma-channel@420a8000 { + reg = <0x420a8000 0x8000>; + interrupts = ; + }; + + dma-channel@420b0000 { + reg = <0x420b0000 0x8000>; + interrupts = ; + }; + + dma-channel@420b8000 { + reg = <0x420b8000 0x8000>; + interrupts = ; + }; + + dma-channel@420c0000 { + reg = <0x420c0000 0x8000>; + interrupts = ; + }; + + dma-channel@420c8000 { + reg = <0x420c8000 0x8000>; + interrupts = ; + }; + + dma-channel@420d0000 { + reg = <0x420d0000 0x8000>; + interrupts = ; + }; + + dma-channel@420d8000 { + reg = <0x420d8000 0x8000>; + interrupts = ; + }; + + dma-channel@420e0000 { + reg = <0x420e0000 0x8000>; + interrupts = ; + }; + + dma-channel@420e8000 { + reg = <0x420e8000 0x8000>; + interrupts = ; + }; + + dma-channel@420f0000 { + reg = <0x420f0000 0x8000>; + interrupts = ; + }; + + dma-channel@420f8000 { + reg = <0x420f8000 0x8000>; + interrupts = ; + }; + + dma-channel@42100000 { + reg = <0x42100000 0x8000>; + interrupts = ; + }; + + dma-channel@42108000 { + reg = <0x42108000 0x8000>; + interrupts = ; + }; + + dma-channel@42110000 { + reg = <0x42110000 0x8000>; + interrupts = ; + }; + + dma-channel@42118000 { + reg = <0x42118000 0x8000>; + interrupts = ; + }; + + dma-channel@42120000 { + reg = <0x42120000 0x8000>; + interrupts = ; + }; + + dma-channel@42128000 { + reg = <0x42128000 0x8000>; + interrupts = ; + }; + + dma-channel@42130000 { + reg = <0x42130000 0x8000>; + interrupts = ; + }; + + dma-channel@42138000 { + reg = <0x42138000 0x8000>; + interrupts = ; + }; + + dma-channel@42140000 { + reg = <0x42140000 0x8000>; + interrupts = ; + }; + + dma-channel@42148000 { + reg = <0x42148000 0x8000>; + interrupts = ; + }; + + dma-channel@42150000 { + reg = <0x42150000 0x8000>; + interrupts = ; + }; + + dma-channel@42158000 { + reg = <0x42158000 0x8000>; + interrupts = ; + }; + + dma-channel@42160000 { + reg = <0x42160000 0x8000>; + interrupts = ; + }; + + dma-channel@42168000 { + reg = <0x42168000 0x8000>; + interrupts = ; + }; + + dma-channel@42170000 { + reg = <0x42170000 0x8000>; + interrupts = ; + }; + + dma-channel@42178000 { + reg = <0x42178000 0x8000>; + interrupts = ; + }; + + dma-channel@42180000 { + reg = <0x42180000 0x8000>; + interrupts = ; + }; + + dma-channel@42188000 { + reg = <0x42188000 0x8000>; + interrupts = ; + }; + + dma-channel@42190000 { + reg = <0x42190000 0x8000>; + interrupts = ; + }; + + dma-channel@42198000 { + reg = <0x42198000 0x8000>; + interrupts = ; + }; + + dma-channel@421a0000 { + reg = <0x421a0000 0x8000>; + interrupts = ; + }; + + dma-channel@421a8000 { + reg = <0x421a8000 0x8000>; + interrupts = ; + }; + + dma-channel@421b0000 { + reg = <0x421b0000 0x8000>; + interrupts = ; + }; + + dma-channel@421b8000 { + reg = <0x421b8000 0x8000>; + interrupts = ; + }; + + dma-channel@421c0000 { + reg = <0x421c0000 0x8000>; + interrupts = ; + }; + + dma-channel@421c8000 { + reg = <0x421c8000 0x8000>; + interrupts = ; + }; + + dma-channel@421d0000 { + reg = <0x421d0000 0x8000>; + interrupts = ; + }; + + dma-channel@421d8000 { + reg = <0x421d8000 0x8000>; + interrupts = ; + }; + + dma-channel@421e0000 { + reg = <0x421e0000 0x8000>; + interrupts = ; + }; + + dma-channel@421e8000 { + reg = <0x421e8000 0x8000>; + interrupts = ; + }; + + dma-channel@421f0000 { + reg = <0x421f0000 0x8000>; + interrupts = ; + }; + + dma-channel@421f8000 { + reg = <0x421f8000 0x8000>; + interrupts = ; + }; + + dma-channel@42200000 { + reg = <0x42200000 0x8000>; + interrupts = ; + }; + + dma-channel@42208000 { + reg = <0x42208000 0x8000>; + interrupts = ; + }; }; edma3: dma-controller@42210000 { compatible = "fsl,imx95-edma5"; reg = <0x42210000 0x210000>; #dma-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; dma-channels = <64>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "dma"; + + dma-channel@42220000 { + reg = <0x42220000 0x8000>; + interrupts = ; + }; + + dma-channel@42228000 { + reg = <0x42228000 0x8000>; + interrupts = ; + }; + + dma-channel@42230000 { + reg = <0x42230000 0x8000>; + interrupts = ; + }; + + dma-channel@42238000 { + reg = <0x42238000 0x8000>; + interrupts = ; + }; + + dma-channel@42240000 { + reg = <0x42240000 0x8000>; + interrupts = ; + }; + + dma-channel@42248000 { + reg = <0x42248000 0x8000>; + interrupts = ; + }; + + dma-channel@42250000 { + reg = <0x42250000 0x8000>; + interrupts = ; + }; + + dma-channel@42258000 { + reg = <0x42258000 0x8000>; + interrupts = ; + }; + + dma-channel@42260000 { + reg = <0x42260000 0x8000>; + interrupts = ; + }; + + dma-channel@42268000 { + reg = <0x42268000 0x8000>; + interrupts = ; + }; + + dma-channel@42270000 { + reg = <0x42270000 0x8000>; + interrupts = ; + }; + + dma-channel@42278000 { + reg = <0x42278000 0x8000>; + interrupts = ; + }; + + dma-channel@42280000 { + reg = <0x42280000 0x8000>; + interrupts = ; + }; + + dma-channel@42288000 { + reg = <0x42288000 0x8000>; + interrupts = ; + }; + + dma-channel@42290000 { + reg = <0x42290000 0x8000>; + interrupts = ; + }; + + dma-channel@42298000 { + reg = <0x42298000 0x8000>; + interrupts = ; + }; + + dma-channel@422a0000 { + reg = <0x422a0000 0x8000>; + interrupts = ; + }; + + dma-channel@422a8000 { + reg = <0x422a8000 0x8000>; + interrupts = ; + }; + + dma-channel@422b0000 { + reg = <0x422b0000 0x8000>; + interrupts = ; + }; + + dma-channel@422b8000 { + reg = <0x422b8000 0x8000>; + interrupts = ; + }; + + dma-channel@422c0000 { + reg = <0x422c0000 0x8000>; + interrupts = ; + }; + + dma-channel@422c8000 { + reg = <0x422c8000 0x8000>; + interrupts = ; + }; + + dma-channel@422d0000 { + reg = <0x422d0000 0x8000>; + interrupts = ; + }; + + dma-channel@422d8000 { + reg = <0x422d8000 0x8000>; + interrupts = ; + }; + + dma-channel@422e0000 { + reg = <0x422e0000 0x8000>; + interrupts = ; + }; + + dma-channel@422e8000 { + reg = <0x422e8000 0x8000>; + interrupts = ; + }; + + dma-channel@422f0000 { + reg = <0x422f0000 0x8000>; + interrupts = ; + }; + + dma-channel@422f8000 { + reg = <0x422f8000 0x8000>; + interrupts = ; + }; + + dma-channel@42300000 { + reg = <0x42300000 0x8000>; + interrupts = ; + }; + + dma-channel@42308000 { + reg = <0x42308000 0x8000>; + interrupts = ; + }; + + dma-channel@42310000 { + reg = <0x42310000 0x8000>; + interrupts = ; + }; + + dma-channel@42318000 { + reg = <0x42318000 0x8000>; + interrupts = ; + }; + + dma-channel@42320000 { + reg = <0x42320000 0x8000>; + interrupts = ; + }; + + dma-channel@42328000 { + reg = <0x42328000 0x8000>; + interrupts = ; + }; + + dma-channel@42330000 { + reg = <0x42330000 0x8000>; + interrupts = ; + }; + + dma-channel@42338000 { + reg = <0x42338000 0x8000>; + interrupts = ; + }; + + dma-channel@42340000 { + reg = <0x42340000 0x8000>; + interrupts = ; + }; + + dma-channel@42348000 { + reg = <0x42348000 0x8000>; + interrupts = ; + }; + + dma-channel@42350000 { + reg = <0x42350000 0x8000>; + interrupts = ; + }; + + dma-channel@42358000 { + reg = <0x42358000 0x8000>; + interrupts = ; + }; + + dma-channel@42360000 { + reg = <0x42360000 0x8000>; + interrupts = ; + }; + + dma-channel@42368000 { + reg = <0x42368000 0x8000>; + interrupts = ; + }; + + dma-channel@42370000 { + reg = <0x42370000 0x8000>; + interrupts = ; + }; + + dma-channel@42378000 { + reg = <0x42378000 0x8000>; + interrupts = ; + }; + + dma-channel@42380000 { + reg = <0x42380000 0x8000>; + interrupts = ; + }; + + dma-channel@42388000 { + reg = <0x42388000 0x8000>; + interrupts = ; + }; + + dma-channel@42390000 { + reg = <0x42390000 0x8000>; + interrupts = ; + }; + + dma-channel@42398000 { + reg = <0x42398000 0x8000>; + interrupts = ; + }; + + dma-channel@423a0000 { + reg = <0x423a0000 0x8000>; + interrupts = ; + }; + + dma-channel@423a8000 { + reg = <0x423a8000 0x8000>; + interrupts = ; + }; + + dma-channel@423b0000 { + reg = <0x423b0000 0x8000>; + interrupts = ; + }; + + dma-channel@423b8000 { + reg = <0x423b8000 0x8000>; + interrupts = ; + }; + + dma-channel@423c0000 { + reg = <0x423c0000 0x8000>; + interrupts = ; + }; + + dma-channel@423c8000 { + reg = <0x423c8000 0x8000>; + interrupts = ; + }; + + dma-channel@423d0000 { + reg = <0x423d0000 0x8000>; + interrupts = ; + }; + + dma-channel@423d8000 { + reg = <0x423d8000 0x8000>; + interrupts = ; + }; + + dma-channel@423e0000 { + reg = <0x423e0000 0x8000>; + interrupts = ; + }; + + dma-channel@423e8000 { + reg = <0x423e8000 0x8000>; + interrupts = ; + }; + + dma-channel@423f0000 { + reg = <0x423f0000 0x8000>; + interrupts = ; + }; + + dma-channel@423f8000 { + reg = <0x423f8000 0x8000>; + interrupts = ; + }; + + dma-channel@42400000 { + reg = <0x42400000 0x8000>; + interrupts = ; + }; + + dma-channel@42408000 { + reg = <0x42408000 0x8000>; + interrupts = ; + }; + + dma-channel@42410000 { + reg = <0x42410000 0x8000>; + interrupts = ; + }; + + dma-channel@42418000 { + reg = <0x42418000 0x8000>; + interrupts = ; + }; }; mu7: mailbox@42430000 { -- 2.51.0