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([171.245.4.151]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc7dab424e8sm853583a12.32.2026.09.30.06.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 06:02:34 -0700 (PDT) From: Nguyen Minh Tien To: Wilken Gottwalt Cc: Bjorn Andersson , Baolin Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Andre Przywara , Bastian Germann , linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] riscv: dts: allwinner: d1-t113: Add the hardware spinlock Date: Wed, 30 Sep 2026 20:02:21 +0700 Message-Id: <20260930130221.129529-1-tien.nguyenminh@embeddedlinux.blog> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260927132707.5f484946@posteo.net> References: <20260927025626.69614-1-tien.nguyenminh@embeddedlinux.blog> <20260927025626.69614-4-tien.nguyenminh@embeddedlinux.blog> <20260927132707.5f484946@posteo.net> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Wilken, > Wouldn't it make more sense to add the "allwinner,sun20i-d1-hwspinlock" line to > the driver in the sun6i_hwspinlock_ids struct, drop > "allwinner,sun6i-a31-hwspinlock" here in the D1 device tree and update the yaml > file accordingly? Thanks for looking at it. Bjorn hasn't replied yet, so I looked a bit more at the naming. I'd like to keep the A31 fallback: it's the usual pattern, other blocks in this dtsi do the same (timer, I2S, LED controller), and Conor already acked the binding in 2/3. If Bjorn prefers a driver entry instead, I'm fine to change it. > Oh, and I may be able to test it against the D1, I own a Sipeed Nezha. That would be great. You don't need FreeRTOS for it: I tested with a small Linux module that takes each lock and checks the status register. I can clean it up for the single-core D1 and send it. Thanks, Tien