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([171.245.4.151]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4ee4d0af2sm308136a91.2.2026.09.30.08.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 08:48:57 -0700 (PDT) From: Nguyen Minh Tien To: Mauro Carvalho Chehab , Hans Verkuil Cc: Nguyen Minh Tien , Sakari Ailus , Laurent Pinchart , Paul Kocialkowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] riscv: dts: allwinner: d1s-t113: Add the CSIC node Date: Wed, 30 Sep 2026 22:48:35 +0700 Message-Id: <20260930154835.402684-4-tien.nguyenminh@embeddedlinux.blog> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260930154835.402684-1-tien.nguyenminh@embeddedlinux.blog> References: <20260930154835.402684-1-tien.nguyenminh@embeddedlinux.blog> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the CSIC node to the dtsi shared by the D1, D1s and T113, with the pin groups of its parallel input. MCLK has its own group, for the sensor node. Signed-off-by: Nguyen Minh Tien --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 13b1e57166..dd4c873457 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -70,6 +70,20 @@ clk_pg11_pin: clk-pg11-pin { function = "clk"; }; + /omit-if-no-ref/ + csi0_8bit_pins: csi0-8bit-pins { + pins = "PE0", "PE1", "PE2", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "ncsi0"; + }; + + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE3"; + function = "ncsi0"; + }; + /omit-if-no-ref/ dsi_4lane_pins: dsi-4lane-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", @@ -997,6 +1011,23 @@ tcon_tv0_out_tcon_top_hdmi: endpoint { }; }; + csi: csi@5800000 { + compatible = "allwinner,sun20i-d1-csi"; + reg = <0x5800000 0x400000>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_TOP>, + <&ccu CLK_MBUS_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi0_8bit_pins>; + status = "disabled"; + }; + ppu: power-controller@7001000 { compatible = "allwinner,sun20i-d1-ppu"; reg = <0x7001000 0x1000>; -- 2.34.1