Re: [PATCH 3/3] riscv: dts: allwinner: d1s-t113: Add the CSIC node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dts: missing mandatory 'port' child node in csi@5800000
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commit 748644695d3510624f461ae96dba4a0eda614827
Author: Nguyen Minh Tien <tien.nguyenminh@embeddedlinux.blog>

riscv: dts: allwinner: d1s-t113: Add the CSIC node

Add the CSIC node to the dtsi shared by the D1, D1s and T113, with the
pin groups of its parallel input. MCLK has its own group, for the sensor
node.

> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> index 13b1e57166040..dd4c873457e22 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

[ ... ]

> @@ -997,6 +1011,23 @@ tcon_tv0_out_tcon_top_hdmi: endpoint {
>  			};
>  		};
>  
> +		csi: csi@5800000 {
> +			compatible = "allwinner,sun20i-d1-csi";
> +			reg = <0x5800000 0x400000>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(95) IRQ_TYPE_LEVEL_HIGH>,
> +				     <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>,
> +				     <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_LEVEL_HIGH>,
> +				     <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_CSI>,
> +				 <&ccu CLK_CSI_TOP>,
> +				 <&ccu CLK_MBUS_CSI>;
> +			clock-names = "bus", "mod", "ram";
> +			resets = <&ccu RST_BUS_CSI>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&csi0_8bit_pins>;
> +			status = "disabled";
> +		};

[Severity: Low]
Will this missing child node cause make dtbs_check validation to fail?

The allwinner,sun20i-d1-csi device tree binding explicitly mandates the port
property, but the csi node is defined here without the mandatory port child
node.

> +
>  		ppu: power-controller@7001000 {

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Sashiko AI review · https://sashiko.dev/#/patchset/20260930154835.402684-1-tien.nguyenminh@embeddedlinux.blog?part=3