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[90.182.112.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a01ccd1566sm18147705e9.2.2026.09.30.08.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 08:12:49 -0700 (PDT) Date: Wed, 30 Sep 2026 17:12:48 +0200 From: Joshua Crofts To: Fabrice Gasnier Cc: Jonathan Cameron , David Lechner , Nuno =?ISO-8859-1?Q?S=E1?= , "Andy Shevchenko" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Marek Vasut , , , , , , Cheick Traore , Olivier Moysan Subject: Re: [PATCH v3 09/15] iio: adc: stm32-adc: add support for stm32mp23 Message-ID: <20260930171248.00004562@gmail.com> In-Reply-To: <20260930-adc-stm32mp25-v1-v3-9-406834430d72@foss.st.com> References: <20260930-adc-stm32mp25-v1-v3-0-406834430d72@foss.st.com> <20260930-adc-stm32mp25-v1-v3-9-406834430d72@foss.st.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 30 Sep 2026 16:18:30 +0200 Fabrice Gasnier wrote: > Add support for ADC on STM32MP23 SoC. It has 3 ADCs, split into two blocks: > - ADC1 & ADC2 are tightly coupled. > - ADC3 is managed independently. > > It is quite similar to STM32MP25 ADC, except for the trigger list. TIM20 > triggers have been removed. So, handle the differences with a dedicated > compatible and compatible data. > > Co-developed-by: Cheick Traore > Signed-off-by: Cheick Traore > Co-developed-by: Olivier Moysan > Signed-off-by: Olivier Moysan > Signed-off-by: Fabrice Gasnier > --- > Changes in v3: > - Style: Wrap core ID table to 100 chars. > > Changes in v2: > - New patch, split as advised by Andy: one patch for this new SoC > --- > drivers/iio/adc/stm32-adc-core.c | 1 + > drivers/iio/adc/stm32-adc.c | 112 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 113 insertions(+) > > diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c > index bb8b53f52914..f94cc6fe4c02 100644 > --- a/drivers/iio/adc/stm32-adc-core.c > +++ b/drivers/iio/adc/stm32-adc-core.c > @@ -936,6 +936,7 @@ static const struct of_device_id stm32_adc_of_match[] = { > { .compatible = "st,stm32h7-adc-core", .data = (void *)&stm32h7_adc_priv_cfg }, > { .compatible = "st,stm32mp1-adc-core", .data = (void *)&stm32mp1_adc_priv_cfg }, > { .compatible = "st,stm32mp13-adc-core", .data = (void *)&stm32mp13_adc_priv_cfg }, > + { .compatible = "st,stm32mp23-adc-core", .data = (void *)&stm32mp25_adc_priv_cfg }, > { .compatible = "st,stm32mp25-adc-core", .data = (void *)&stm32mp25_adc_priv_cfg }, > { } > }; > diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c > index 33e41505b2e9..210b76b21d13 100644 > --- a/drivers/iio/adc/stm32-adc.c > +++ b/drivers/iio/adc/stm32-adc.c > @@ -563,6 +563,64 @@ static const struct stm32_adc_regspec stm32h7_adc_regspec = { > .smp_bits = stm32h7_smp_bits, > }; > > +/* STM32MP23 external trigger sources for ADC1 and ADC2 */ > +static struct stm32_adc_trig_info stm32mp23_adc1_adc2_trigs[] = { This should be const, the trigs field is marked const in stm32_adc_cfg. > + { TIM1_TRGO, STM32_EXT0 }, > + { TIM1_TRGO2, STM32_EXT1 }, > + { TIM8_TRGO, STM32_EXT2 }, > + { TIM8_TRGO2, STM32_EXT3 }, > + { TIM2_TRGO, STM32_EXT6 }, > + { TIM3_TRGO, STM32_EXT7 }, > + { TIM4_TRGO, STM32_EXT8 }, > + { TIM5_TRGO, STM32_EXT9 }, > + { TIM6_TRGO, STM32_EXT10 }, > + { TIM15_TRGO, STM32_EXT11 }, > + { TIM1_CH1, STM32_EXT12 }, > + { TIM1_CH2, STM32_EXT13 }, > + { TIM1_CH3, STM32_EXT14 }, > + { TIM2_CH2, STM32_EXT18 }, > + { TIM3_CH4, STM32_EXT19 }, > + { TIM4_CH4, STM32_EXT20 }, > + { TIM5_CH1, STM32_EXT21 }, > + { TIM12_CH1, STM32_EXT22 }, > + { LPTIM1_CH1, STM32_EXT24 }, > + { LPTIM2_CH1, STM32_EXT25 }, > + { LPTIM3_CH1, STM32_EXT26 }, > + { LPTIM4_CH1, STM32_EXT27 }, > + { LPTIM5_OUT, STM32_EXT28 }, > + { } > +}; > + > +/* STM32MP23 external trigger sources for ADC3 */ > +static struct stm32_adc_trig_info stm32mp23_adc3_trigs[] = { Same here. -- Kind regards, Joshua Crofts