From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFE1148F827; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; cv=none; b=XySM5GJ1LvT1EzGzgnoDzfW+NKptNIF5XAZH2hi+KZPDwYSgKLi9JdDsfECr5+Lfyt6GOymV+m3an2BypVi35+NOCnsSE8ZXi0L1lKGno3a9UqU5F6Nipl/Dk4pctfaDh0Iaw3alyBwXeRyfuoeJgKoM8NCBtiRqmDmUrBkxBF4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858460; c=relaxed/simple; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ShRDg6Nu8BxeunwK8NTImsVbpZzRPLwOg2dO9gFOCN80DVbpGrqPGFNmVdh6mEZmOBu6nYaDUgrd4ooZ1vpnbN4+3TcyqyHTI0xKqO7mikJIFlYshZPwcJAm4f/PRPw0P84MC4CWB15RC26irHwbMrgLf3f3w4gBtzwqGftFlr0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NAY5v30S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NAY5v30S" Received: by smtp.kernel.org (Postfix) with ESMTPS id 68761C4AF1C; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NAY5v30SwqDl2eaxP6g0qGMcRQvQTwEFtxTF3loIjcOEMkfPPTxH1ZqKpj5Bd2vO+ 2CohcSEy4dwkTBXgSnrKEEJzIvGXRMoeCJJoxvkRpK1QCS74WFlvFEEzQVa7133H5t fXrHoI239EgtqNNm61+GOM5mz3WK5eqieahoCmwrR1GrwkSf+riJGFQfsIj/vIftW5 v2wG+vcqcmP6Z6/M5J0CeEOKbwkEUHNDwhx5Q2fxZl065guOR0cN37SfOoZSxkde1h l2erXJsQT7EEWysDAQXRyKlXbu93iRcphss6SU7xRaPNyTRmk6PIJ4sWGSwJefHlJ2 8Hy6SZiC1/q9Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA71CA5FD4; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:52 +0800 Subject: [PATCH v9 03/15] dt-bindings: clock: add Ambarella CV75 RCT Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261001-cv75-v5-v9-3-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=2969; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=gEKr05f9YAOrNVHJfKB47io9QNiMkJyDyO/ZJBUGYg0=; b=u7dATT7wovn/IzB7hOxdMtQfu2TUxzRgNkKQ39Z1EcHYb35bAClImZoJ8ho3BL/DMU+yHDbEA CPIgGMCt6wNBF6lEORnSXvvSdijqmTcbHfSanh6jfTOQUvRI8WcsCxC X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 RCT clock controller and the clock ID header used by DT consumers. Document #reset-cells for the RCT reset-provider role. Soft-reset line IDs and the reset provider driver are deferred; this series has no resets= consumers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../bindings/clock/ambarella,cv75-rct.yaml | 64 ++++++++++++++++++++++ include/dt-bindings/clock/ambarella,cv75-rct.h | 14 +++++ 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml new file mode 100644 index 000000000000..be89bd75f9e2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ambarella,cv75-rct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 RCT Clock Controller + +maintainers: + - Long Zhao + +description: | + The RCT (Reset and Clock Tree) block on the Ambarella CV75 SoC provides + PLLs, clock muxes, dividers and soft-reset controls for on-chip + peripherals. + + The same register region is also exposed as a syscon for other SoC + blocks (e.g. pin drive-strength), hence the "syscon" compatible. + + Clock indices are defined in include/dt-bindings/clock/ambarella,cv75-rct.h. + +properties: + + compatible: + items: + - const: ambarella,cv75-rct + - const: syscon + + reg: + maxItems: 1 + + clocks: + description: Reference crystal oscillator (typically 24 MHz) + maxItems: 1 + + clock-names: + const: osc + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ed080000 { + compatible = "ambarella,cv75-rct", "syscon"; + reg = <0xed080000 0x1000>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/ambarella,cv75-rct.h b/include/dt-bindings/clock/ambarella,cv75-rct.h new file mode 100644 index 000000000000..b3e965b4ff2e --- /dev/null +++ b/include/dt-bindings/clock/ambarella,cv75-rct.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 Ambarella, Inc. + */ + +#ifndef _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H +#define _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H + +#define CV75_GCLK_UART0 0 +#define CV75_GCLK_CORE 1 +#define CV75_GCLK_AHB 2 +#define CV75_GCLK_APB 3 + +#endif -- 2.34.1