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[103.229.18.19]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2e300b851b9sm5152715ad.78.2026.09.30.22.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 22:23:31 -0700 (PDT) From: Mayuresh Chitale To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Greg KH , Alexander Shishkin , Ian Rogers Cc: Anup Patel , Alexandre Ghiti , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Mark Rutland , Jiri Olsa , Adrian Hunter , Mayuresh Chitale , Anup Patel , Atish Patra , Andrew Jones , Sunil V L , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mayuresh Chitale , Zane Leung Subject: [PATCH v6 01/14] dt-bindings: Add RISC-V trace component bindings Date: Thu, 1 Oct 2026 10:52:12 +0530 Message-ID: <20261001052243.3042627-2-mayuresh.chitale@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001052243.3042627-1-mayuresh.chitale@oss.qualcomm.com> References: <20261001052243.3042627-1-mayuresh.chitale@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDAxMDAyMSBTYWx0ZWRfX10weUt7ZQgOD 1sUag2sKwwLhdlCVZ5wORK5aABy+uYy3AYl6WJc88xOEBcgMsozQyVHkvuqvVuQOo2J+vRiYGhY QRCBmTDznnR2OzXCvNn+ksUl2hg9Ov8= X-Authority-Analysis: v=2.4 cv=OozaWC/t c=1 sm=1 tr=0 ts=6abdee56 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=W-_n0kkjAAAA:8 a=f9mqD-BOXdQ1R_-L-AkA:9 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 a=qeNa2pbTr82C0GpJEZFS:22 X-Proofpoint-ORIG-GUID: ajOKnktfJImkYKPkzUWnXyBfyF93I7-V X-Proofpoint-GUID: ajOKnktfJImkYKPkzUWnXyBfyF93I7-V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDAxMDAyMSBTYWx0ZWRfXwGGjqBMV1dRw 1nfgQ6YqZiV/Uedlvm4/GHofXMdA0ZWR+kaTw8k8DonaVrZXQoIKz98y4uiNXzXTCIE6LnMbqWg Gp2uBr/lzorD4biS0EZKfLGFIzP9BhWnJmasC+zj9gljcQp6FEgFowTLMpXLY1gu22VkZnpopCR G3O2825/64EebbP/751ztgl/WYmmTmSldE2+UA2Zvy6/iZFfGjekVo1soohm3Kscr0MCUac2yIX 4RoOqf4nvJ114jfwNDx6LcOOTigrRhNNwBXk85PoBa0OZIsp+Ah4lN4/gjJ5QWBr8DA8rAd9i3X Qc3ekbYpjsYzlXbYW1db+U7wUyO8gyA2UkGqLhCTbU6/QCBE1TIQNBaMiQMikjjZPSCo+VwXgOO ZVaTSnHxDdbjmOxR9VRhvNaTLzyhm70L2elEDk5D4/kCobtahG9/KW3uJVRpffXXWV8etfeJwpC nTUuJx9eWvtlFb5HPNg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-01_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610010021 From: Anup Patel Add device tree bindings for the memory mapped RISC-V trace components which support both the RISC-V efficient trace (E-trace) protocol and the RISC-V Nexus-based trace (N-trace) protocol. The RISC-V trace components are defined by the RISC-V trace control interface specification. Signed-off-by: Anup Patel Reviewed-by: Rob Herring (Arm) Signed-off-by: Mayuresh Chitale --- .../bindings/riscv/riscv,trace-component.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml diff --git a/Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml b/Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml new file mode 100644 index 000000000000..bb519bc4a163 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/riscv,trace-component.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Trace Component + +maintainers: + - Anup Patel + +description: + The RISC-V trace control interface specification standard memory mapped + components (or devices) which support both the RISC-V efficient trace + (E-trace) protocol and the RISC-V Nexus-based trace (N-trace) protocol. + The RISC-V trace components have implementation specific directed acyclic + graph style interdependency where output of one component serves as input + to another component and certain components (such as funnel) can take inputs + from multiple components. The type and version of a RISC-V trace component + can be discovered from it's IMPL memory mapped register hence component + specific compatible strings are not needed. + +properties: + compatible: + items: + - enum: + - qemu,trace-component + - const: riscv,trace-component + + reg: + maxItems: 1 + + cpus: + maxItems: 1 + description: + phandle to the cpu to which the RISC-V trace component is bound. + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + patternProperties: + '^port(@[0-7])?$': + description: Input connections from RISC-V trace component + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + patternProperties: + '^port(@[0-7])?$': + description: Output connections from RISC-V trace component + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + +anyOf: + - required: [ in-ports ] + - required: [ out-ports ] + +unevaluatedProperties: false + +examples: + - | + // Example 1 (Per-hart encoder and ramsink components): + + trace@c000000 { + compatible = "qemu,trace-component", "riscv,trace-component"; + reg = <0xc000000 0x1000>; + cpus = <&CPU0>; + + out-ports { + port { + CPU0_ENCODER_OUTPUT: endpoint { + remote-endpoint = <&CPU0_RAMSINK_INPUT>; + }; + }; + }; + }; + + trace@c001000 { + compatible = "qemu,trace-component", "riscv,trace-component"; + reg = <0xc001000 0x1000>; + cpus = <&CPU0>; + + in-ports { + port { + CPU0_RAMSINK_INPUT: endpoint { + }; + }; + }; + }; + + trace@c002000 { + compatible = "qemu,trace-component", "riscv,trace-component"; + reg = <0xc002000 0x1000>; + cpus = <&CPU1>; + + out-ports { + port { + CPU1_ENCODER_OUTPUT: endpoint { + remote-endpoint = <&CPU1_RAMSINK_INPUT>; + }; + }; + }; + }; + + trace@c003000 { + compatible = "qemu,trace-component", "riscv,trace-component"; + reg = <0xc003000 0x1000>; + cpus = <&CPU1>; + + in-ports { + port { + CPU1_RAMSINK_INPUT: endpoint { + }; + }; + }; + }; + +... -- 2.43.0