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From: sashiko-bot@kernel.org
To: "George Moussalem" <george.moussalem@outlook.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v4 3/8] arm64: dts: qcom: ipq5424: Flatten usb controller nodes
Date: Thu, 01 Oct 2026 08:04:45 +0000	[thread overview]
Message-ID: <20261001080446.5EFA51F00898@smtp.kernel.org> (raw)
In-Reply-To: <20261001-ipq-flatten-usb-v4-3-486a4d5ede30@outlook.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: IPQ5424 USB clocks and interrupts order violates qcom,snps-dwc3 schema
--

commit 37ae00028e39229f3da1503fa9411f44830ec187
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5424: Flatten usb controller nodes

Flatten usb controller nodes and update to using latest bindings and
flattened driver approach.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 23f851e9241fe..b1bfe31227e76 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
[ ... ]
> @@ -640,12 +640,9 @@ qusb_phy_1: phy@71000 {
>  			status = "disabled";
>  		};
>  
> -		usb2: usb2@1ef8800 {
> -			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> -			reg = <0 0x01ef8800 0 0x400>;
> -			#address-cells = <2>;
> -			#size-cells = <2>;
> -			ranges;
> +		usb2: usb2@1e00000 {
> +			compatible = "qcom,ipq5424-dwc3", "qcom,snps-dwc3";
> +			reg = <0 0x01e00000 0 0xfc100>;
>  
>  			clocks = <&gcc GCC_USB1_MASTER_CLK>,
>  				 <&gcc GCC_USB1_SLEEP_CLK>,

[Severity: Low]
Does changing the compatible string to qcom,snps-dwc3 cause a dtbs_check
validation failure here?

The existing array sequence for clocks in this node does not match the strict
ordering (cfg_noc, core, iface, sleep, mock_utmi) mandated by the newly
applied qcom,snps-dwc3 schema.

[ ... ]
> @@ -664,33 +661,31 @@ usb2: usb2@1ef8800 {
>  			assigned-clock-rates = <200000000>,
>  					       <24000000>;
>  
> -			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts-extended = <&intc GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>  					  "qusb2_phy",
>  					  "dm_hs_phy_irq",
>  					  "dp_hs_phy_irq";

[Severity: Low]
Is the order of interrupts correct for the new schema?

The newly applied qcom,snps-dwc3 schema dictates that dp_hs_phy_irq must be
declared before dm_hs_phy_irq, but they are listed in the reverse order here.
This will cause dtbs_check to fail.

[ ... ]
> -		usb3: usb3@8af8800 {
> -			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> -			reg = <0 0x08af8800 0 0x400>;
> -
> -			#address-cells = <2>;
> -			#size-cells = <2>;
> -			ranges;
> +		usb3: usb3@8a00000 {
> +			compatible = "qcom,ipq5424-dwc3", "qcom,snps-dwc3";
> +			reg = <0 0x08a00000 0 0xfc100>;
>  
>  			clocks = <&gcc GCC_USB0_MASTER_CLK>,
>  				 <&gcc GCC_USB0_SLEEP_CLK>,

[Severity: Low]
Does changing the compatible string to qcom,snps-dwc3 cause a dtbs_check
validation failure here?

The existing array sequence for clocks in this node does not match the strict
ordering (cfg_noc, core, iface, sleep, mock_utmi) mandated by the newly
applied qcom,snps-dwc3 schema.

[ ... ]
> @@ -771,34 +762,31 @@ usb3: usb3@8af8800 {
>  			assigned-clock-rates = <200000000>,
>  					       <24000000>;
>  
> -			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts-extended = <&intc GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
>  					  "qusb2_phy",
>  					  "dm_hs_phy_irq",
>  					  "dp_hs_phy_irq";

[Severity: Low]
Is the order of interrupts correct for the new schema?

The newly applied qcom,snps-dwc3 schema dictates that dp_hs_phy_irq must be
declared before dm_hs_phy_irq, but they are listed in the reverse order here.
This will cause dtbs_check to fail.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261001-ipq-flatten-usb-v4-0-486a4d5ede30@outlook.com?part=3

  reply	other threads:[~2026-10-01  8:04 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01  7:53 [PATCH v4 0/8] Flatten USB Controller Nodes on IPQ SoCs George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 1/8] arm64: dts: qcom: ipq5018: Flatten usb controller node George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 2/8] arm64: dts: qcom: ipq5332: " George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 3/8] arm64: dts: qcom: ipq5424: Flatten usb controller nodes George Moussalem via B4 Relay
2026-10-01  8:04   ` sashiko-bot [this message]
2026-10-01  7:53 ` [PATCH v4 4/8] arm64: dts: qcom: ipq6018: move DR mode to board DTS George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 5/8] arm64: dts: qcom: ipq6018: Flatten usb controller nodes George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 6/8] arm64: dts: qcom: ipq8074: move DR mode to board DTS George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 7/8] arm64: dts: qcom: ipq8074: Flatten usb controller nodes George Moussalem via B4 Relay
2026-10-01  7:53 ` [PATCH v4 8/8] arm64: dts: qcom: ipq9574: Flatten usb controller node George Moussalem via B4 Relay

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