From: sashiko-bot@kernel.org
To: "Robert Marko" <robert.marko@sartura.hr>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 5/5] net: phy: mxl-gpy: support MxL86211C lane mapping
Date: Thu, 01 Oct 2026 12:23:32 +0000 [thread overview]
Message-ID: <20261001122333.4D4381F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260930122305.293686-5-robert.marko@sartura.hr>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] net: phy: mxl-gpy: potential overwrite of upper bits in VSPEC1_LANE_ASP_MAP
--
commit 6afd4cf52cade8d4300f55c200c7e05630214098
Author: Robert Marko <robert.marko@sartura.hr>
net: phy: mxl-gpy: support MxL86211C lane mapping
Configure the MxL86211C physical TPI lane to ASP mapping when it is
described in DTS. MxL86211C supports per lane configuration. Leaves the
hardware reset configuration untouched when the optional property is absent.
> diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c
> index 790075632fc3f..f716da0ffe890 100644
> --- a/drivers/net/phy/mxl-gpy.c
> +++ b/drivers/net/phy/mxl-gpy.c
[ ... ]
> +static int mxl86211c_configure_lane_asp_map(struct phy_device *phydev)
> +{
> + struct device *dev = &phydev->mdio.dev;
> + u32 lane_asp_map[4];
> + u16 val;
> + unsigned int seen = 0;
> + int i, ret;
> +
> + if (!device_property_present(dev, "maxlinear,lane-asp-map"))
> + return 0;
[ ... ]
> + val = FIELD_PREP(VSPEC1_LANE_ASP_MAP_A, lane_asp_map[0]) |
> + FIELD_PREP(VSPEC1_LANE_ASP_MAP_B, lane_asp_map[1]) |
> + FIELD_PREP(VSPEC1_LANE_ASP_MAP_C, lane_asp_map[2]) |
> + FIELD_PREP(VSPEC1_LANE_ASP_MAP_D, lane_asp_map[3]);
> +
> + return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LANE_ASP_MAP,
> + val);
[Severity: Medium]
Does this potentially overwrite upper bits in VSPEC1_LANE_ASP_MAP?
In drivers/net/phy/mxl-gpy.c, within mxl86211c_configure_lane_asp_map(), this
performs a full 16-bit register write instead of a read-modify-write, which
implicitly zeroes any bits outside the 8-bit mapping mask.
If bits 8-15 are used by the hardware for other independent fields, could
clearing them lead to undefined behavior or state corruption?
This path triggers during PHY initialization when the maxlinear,lane-asp-map
device tree property is present. Would it be safer to use phy_modify_mmd()
here to preserve any reserved or unrelated bits?
> +}
> +
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260930122305.293686-1-robert.marko@sartura.hr?part=5
next prev parent reply other threads:[~2026-10-01 12:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 12:22 [PATCH 1/5] dt-bindings: net: maxlinear: add MxL86211C MDIO I/O regulator Robert Marko
2026-09-30 12:22 ` [PATCH 2/5] net: phy: mxl-gpy: " Robert Marko
2026-10-01 12:23 ` sashiko-bot
2026-10-04 13:17 ` netdev-bot+sashiko
2026-09-30 12:22 ` [PATCH 3/5] net: phy: mxl-gpy: release MxL86211C Super Isolate Robert Marko
2026-10-01 12:23 ` sashiko-bot
2026-10-04 13:17 ` netdev-bot+sashiko
2026-09-30 12:22 ` [PATCH 4/5] dt-bindings: net: maxlinear: add MxL86211C lane mapping support Robert Marko
2026-10-01 5:55 ` Krzysztof Kozlowski
2026-10-01 12:14 ` Robert Marko
2026-10-01 12:33 ` Andrew Lunn
2026-10-07 8:49 ` Robert Marko
2026-10-07 13:14 ` Andrew Lunn
2026-10-01 16:25 ` Rob Herring (Arm)
2026-10-04 13:17 ` netdev-bot+sashiko
2026-09-30 12:22 ` [PATCH 5/5] net: phy: mxl-gpy: support MxL86211C lane mapping Robert Marko
2026-09-30 15:35 ` Andrew Lunn
2026-09-30 16:58 ` Robert Marko
2026-10-01 12:23 ` sashiko-bot [this message]
2026-10-04 13:17 ` netdev-bot+sashiko
2026-10-01 12:23 ` [PATCH 1/5] dt-bindings: net: maxlinear: add MxL86211C MDIO I/O regulator sashiko-bot
2026-10-04 13:17 ` netdev-bot+sashiko
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