On Fri, Aug 28, 2026 at 02:56:00AM -0700, Changhuang Liang wrote:
> StarFive JHB100 has many syscon modules, as listed below:
> - pcieep0_ecsr_syscon	(PCIe endpoint 0 externel syscon)
> - pcieep1_ecsr_syscon
> - host0_syscon		(Host0 syscon)
> - host1_syscon
> - husb0_syscon		(Host USB 0 syscon)
> - husb1_syscon
> - husbd0_syscon		(Host USB device 0 syscon)
> - husbd1_syscon
> - husbcmn_syscon	(Host USB common syscon)
> - gpu0_syscon		(GPU0 syscon)
> - gpu1_syscon
> - b2h_syscon		(BMC to Host syscon)
> - h2b_syscon		(Host to BMC syscon)
> - vout_syscon		(Video output syscon)
> - pcierp_ecsr_syscon	(PCIe root port externel syscon)
> - pcierp_syscon		(PCIe root port syscon)
> - usb_syscon
> - npu_syscon
> - per0_syscon		(Peripheral 0 syscon)
> - per1_syscon
> - per2_syscon
> - per3_syscon
> - sys0_syscon		(System 0 syscon)
> - sys1_syscon
> - sys2_syscon
> - strap_syscon
> - sfc0_filter_syscon	(SFC0 filter syscon)
> - sfc1_filter_syscon
> - sfc2_filter_syscon
> 
> Some syscon modules contain PLL, reset, and socinfo nodes
> 
> This series depends on the series:
> https://lore.kernel.org/all/20260807112923.191627-1-changhuang.liang@starfivetech.com/
> 
> changes since v4:
> PATCH 2:
> - Constify name pointer
> - flag ==> flags
> - Use FIELD_GET() and FIELD_PREP()
> - Use DEFINE_SHOW_ATTRIBUTE()
> - Replace of_device_get_match_data() with device_get_match_data().
> - Make the driver compatible with both MFD cell instantiation and
>   direct device tree node probing.
> - select STARFIVE_JHB100_SOCINFO and select MFD_SYSCON
> 
> PATCH 3:
> - The changes in PATCH 2 introduced a conflict with PATCH 3, requiring
>   modifications.
> 
> PATCH 7:
> - Binds directly to the "starfive,jhb100-sys0-syscon" node.
> - Instantiates the sys0 PLL clock driver as an MFD child cell,
>   since the syscon region contains both the revision register
>   and PLL controls.
> - Uses devm_* APIs for automatic resource cleanup.
> 
> v4: https://lore.kernel.org/all/20260809015054.210577-1-changhuang.liang@starfivetech.com/
> v3: https://lore.kernel.org/all/20260521012932.24163-1-changhuang.liang@starfivetech.com/
> v2: https://lore.kernel.org/all/20260512083521.3448-1-changhuang.liang@starfivetech.com/
> V1: https://lore.kernel.org/all/20260403054945.467700-1-changhuang.liang@starfivetech.com/
> 
> Changhuang Liang (8):
>   dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
>   clk: starfive: Add system-0 domain PLL clock driver
>   clk: starfive: Add peripheral-0 domain PLL clock driver
>   clk: starfive: Add Peripheral-1 domain PLL clock driver
>   reset: starfive: Introduce active_low
>   reset: starfive: Add syscon reset driver support
>   soc: starfive: Add socinfo driver for JHB100 SoC
>   riscv: dts: starfive: jhb100: Add syscon nodes

I've applied patches 1 & 7 of this, and included the former in a PR sent
to Brian a few minutes ago. I'll queue patch 8 in my pending content
branch for the jhb100, when you resubmit to resolve the recent driver
feedback, please drop those three patches.

Thanks,
Conor.