Re: [PATCH v2 2/2] riscv: dts: anlogic: drop unused DR1V90 external clocks

[Conor Dooley <conor@kernel.org>]

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On Sat, Oct 03, 2026 at 12:28:40AM +0800, Junhui Liu wrote:
> The external CAN and watchdog clock inputs are not routed on the MLKPAI
> FS01, the only board currently supported. Drop the two fixed-clock
> placeholders from the common dtsi, as fixed clocks require a valid
> clock-frequency property.
> 
> Both clock muxes select their internal parent clocks after reset, so
> the CRU operates correctly without the external inputs. Keep only the
> required oscillator input to the CRU.
> 
> A board using these external clocks should define them in its own
> board-level dts and override the clocks and clock-names properties of
> the CRU node.
> 
> Reported-by: Yixun Lan <dlan@kernel.org>
> Fixes: 7849521aaac2 ("riscv: dts: anlogic: add clocks and CRU for DR1V90")
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>

Per the v1, Brian said he would rebase the clock tree, so I'll just
squash this into the original patch I think.

> ---
>  arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 16 ++--------------
>  1 file changed, 2 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
> index 574c6608aef0..fe85d01563ad 100644
> --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
> +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
> @@ -44,23 +44,11 @@ cpu0_intc: interrupt-controller {
>  	};
>  
>  	clocks {
> -		can_ext: clock-ext-can {
> -			compatible = "fixed-clock";
> -			clock-output-names = "can_ext";
> -			#clock-cells = <0>;
> -		};
> -
>  		osc: clock-osc {
>  			compatible = "fixed-clock";
>  			clock-output-names = "osc";
>  			#clock-cells = <0>;
>  		};
> -
> -		wdt_ext: clock-ext-wdt {
> -			compatible = "fixed-clock";
> -			clock-output-names = "wdt_ext";
> -			#clock-cells = <0>;
> -		};
>  	};
>  
>  	soc {
> @@ -128,8 +116,8 @@ uart1: serial@f8401000 {
>  		cru: clock-controller@f8801000 {
>  			compatible = "anlogic,dr1v90-cru";
>  			reg = <0x0 0xf8801000 0 0x400>;
> -			clocks = <&osc>, <&can_ext>, <&wdt_ext>;
> -			clock-names = "osc", "can_ext", "wdt_ext";
> +			clocks = <&osc>;
> +			clock-names = "osc";
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  		};
> 
> -- 
> 2.55.0
> 

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