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From: sashiko-bot@kernel.org
To: "Kyle Switch" <kyle.switch@motor-comm.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH net-next v23 2/3] net: phy: Add support for Template Control register for PMA
Date: Fri, 02 Oct 2026 09:13:23 +0000	[thread overview]
Message-ID: <20261002091323.C4B331F0089A@smtp.kernel.org> (raw)
In-Reply-To: <20260930194513.663575-3-kyle.switch@motor-comm.com>

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] mdio: uapi: unshifted test mode constants and GENMASK break userspace
- [Low] phy: genphy_c45_template_testmode returns -EOPNOTSUPP instead of -EINVAL
- [Low] phy: vendor-specific 'Template' terminology pollutes generic API
--

commit 60718c14fbea745ac1034f4e3a4c75164fce8bb3
Author: Kyle Switch <kyle.switch@motor-comm.com>

net: phy: Add support for Template Control register for PMA

Add support for the 10GBASE-T PMA Template Test Mode register
field, which allows selecting one of eight test modes (Normal and
TestMode1..TestMode7) used for PHY validation.

> diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
> index 870920311f9a0..c5f5753f7194b 100644
> --- a/drivers/net/phy/phy-c45.c
> +++ b/drivers/net/phy/phy-c45.c
[ ... ]
> @@ -1408,6 +1408,29 @@ int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
>  }
>  EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);
>  
> +/**
> + * genphy_c45_template_testmode - configure template testmode registers
> + * @phydev: target phy_device struct
> + * @test_mode: testmode includes Normal to Test mode 7
> + *
> + * Description: Set template testmode include Normal to Test mode 7
> + *
> + * Return: 0 on success, or a negative error code on failure (e.g. register
> + * read/write error).
> + */
> +int genphy_c45_template_testmode(struct phy_device *phydev, u16 test_mode)

[Severity: Low]
Is it appropriate to use the vendor-specific term Template in the generic
PHY API?

This terminology doesn't appear to exist in the IEEE 802.3 specification
for the 10GBASE-T test mode register (1.132, Clause 45.2.1.75). Using it
here and in the UAPI header may mislead developers using the generic PHY
headers.

> +{
> +	u16 ctrl;
> +
> +	if (test_mode > MDIO_PMA_10GBT_TESTMODE_7)
> +		return -EOPNOTSUPP;

[Severity: Low]
Should this bounds check return -EINVAL instead of -EOPNOTSUPP?

Returning -EOPNOTSUPP implies the hardware doesn't support the test mode
feature at all, while the actual problem here is that the provided
argument is invalid.

> +
> +	ctrl = FIELD_PREP(MDIO_PMA_10GBT_TESTMODE_MASK, test_mode);
> +	return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TESTMODE,
> +			      MDIO_PMA_10GBT_TESTMODE_MASK, ctrl);
> +}
> +EXPORT_SYMBOL_GPL(genphy_c45_template_testmode);
[ ... ]
> diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
> index 06f4bc3c20c71..353ca13c64fca 100644
> --- a/include/uapi/linux/mdio.h
> +++ b/include/uapi/linux/mdio.h
[ ... ]
> @@ -320,6 +321,17 @@
>  /* PMA 10GBASE-R Fast Retrain status and control register. */
>  #define MDIO_PMA_10GBR_FSRT_ENABLE	0x0001	/* Fast retrain enable */
>  
> +/* PMA 10GBASE-T Template Test Mode Register*/
> +#define MDIO_PMA_10GBT_TESTMODE_MASK GENMASK(15, 13) /* Template test mode */
> +#define MDIO_PMA_10GBT_TESTMODE_NORMAL 0x0 /* Template Normal */
> +#define MDIO_PMA_10GBT_TESTMODE_1 0x1 /* Template TestMode1 */

[Severity: Medium]
Will this break compilation for userspace applications since GENMASK is a
kernel-internal macro?

Also, the constants are exported as unshifted values (e.g., 0x1) without a
corresponding shift macro. Since userspace applications don't have access to
FIELD_PREP(), applications attempting to use these constants directly will
erroneously set bit 0 instead of bit 13, leading to silent hardware
misconfiguration.

> +#define MDIO_PMA_10GBT_TESTMODE_2 0x2 /* Template TestMode2 */
> +#define MDIO_PMA_10GBT_TESTMODE_3 0x3 /* Template TestMode3 */
> +#define MDIO_PMA_10GBT_TESTMODE_4 0x4 /* Template TestMode4 */
> +#define MDIO_PMA_10GBT_TESTMODE_5 0x5 /* Template TestMode5 */
> +#define MDIO_PMA_10GBT_TESTMODE_6 0x6 /* Template TestMode6 */
> +#define MDIO_PMA_10GBT_TESTMODE_7 0x7 /* Template TestMode7 */
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260930194513.663575-1-kyle.switch@motor-comm.com?part=2

  reply	other threads:[~2026-10-02  9:13 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-30 19:45 [PATCH net-next v23 0/3] net: phy: Add driver for Motorcomm Quad 2.5GbE phy Kyle Switch
2026-09-30 19:45 ` [PATCH net-next v23 1/3] dt-bindings: net: Document Motorcomm YT8824 PHY package Kyle Switch
2026-10-04 21:10   ` netdev-bot+sashiko
2026-09-30 19:45 ` [PATCH net-next v23 2/3] net: phy: Add support for Template Control register for PMA Kyle Switch
2026-10-02  9:13   ` sashiko-bot [this message]
2026-10-04 21:10   ` netdev-bot+sashiko
2026-09-30 19:45 ` [PATCH net-next v23 3/3] net: phy: Add driver for Motorcomm Quad 2.5GbE phy Kyle Switch
2026-10-01 15:33   ` Jakub Kicinski
2026-10-02  9:13   ` sashiko-bot
2026-10-04 21:10   ` netdev-bot+sashiko

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