From: sashiko-bot@kernel.org
To: "Michał Kopeć" <michal@nozomi.space>
Cc: robh@kernel.org, conor+dt@kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: mediatek: mt8188: Add the MFGCFG phandle to the GPU
Date: Sat, 03 Oct 2026 20:12:27 +0000 [thread overview]
Message-ID: <20261003201227.9D4A21F0089B@smtp.kernel.org> (raw)
In-Reply-To: <20261003200132.866240-4-michal@nozomi.space>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/panfrost: missing GPU timestamp quirk on MT8370
--
commit ad326344199c9c294e6415c92318bcef828d8630
Author: Michał Kopeć <michal@nozomi.space>
arm64: dts: mediatek: mt8188: Add the MFGCFG phandle to the GPU
This commit adds the MFGCFG phandle to the GPU node in the MT8188 device
tree. The GPU driver requires this configuration block to enable the GPU
timestamp counter, which otherwise reads zero.
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 14a320f0c70cb..b4be89bf55bf7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -2266,6 +2266,7 @@ gpu: gpu@13000000 {
> <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
> <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
> interrupt-names = "job", "mmu", "gpu";
> + mediatek,mfgcfg = <&mfgcfg>;
[Severity: Medium]
Since we are enabling the GPU timestamp counter via the MFG configuration
block for the MT8188, does the MT8370 SoC also need its corresponding quirk
updated in the panfrost driver to avoid breaking userspace timestamp queries?
Looking at drivers/gpu/drm/panfrost/panfrost_drv.c, the mediatek_mt8370_data
struct is defined as:
static const struct panfrost_compatible mediatek_mt8370_data = {
.num_supplies = ARRAY_SIZE(default_supplies) - 1,
.supply_names = default_supplies,
.num_pm_domains = 2,
.pm_domain_names = mediatek_pm_domains,
.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
};
This struct lacks .vendor_quirk = panfrost_gpu_mt8188_quirk.
When the driver probes on MT8370 using the mediatek,mt8370-mali compatible,
the missing quirk means the MFG configuration block is never enabled. As a
result, the GPU timestamp counter will read zero on the MT8370 SoC.
Could this be an omission, or is it intentional to skip the vendor quirk
for MT8370?
> nvmem-cells = <&gpu_speedbin>;
> nvmem-cell-names = "speed-bin";
> operating-points-v2 = <&gpu_opp_table>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261003200132.866240-1-michal@nozomi.space?part=3
prev parent reply other threads:[~2026-10-03 20:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-03 20:01 [PATCH 0/3] drm/panfrost: Enable the GPU timestamp counter on MT8188 Michał Kopeć
2026-10-03 20:01 ` [PATCH 1/3] dt-bindings: gpu: mali-bifrost: Add the MT8188 MFGCFG phandle Michał Kopeć
2026-10-09 7:01 ` Krzysztof Kozlowski
2026-10-03 20:01 ` [PATCH 2/3] drm/panfrost: Enable the GPU timestamp counter on MT8188 Michał Kopeć
2026-10-03 20:10 ` sashiko-bot
2026-10-03 20:01 ` [PATCH 3/3] arm64: dts: mediatek: mt8188: Add the MFGCFG phandle to the GPU Michał Kopeć
2026-10-03 20:12 ` sashiko-bot [this message]
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